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5.116 timer issues (gate control)

 
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newguy



Joined: 24 Jun 2004
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5.116 timer issues (gate control)
PostPosted: Wed Oct 18, 2023 9:43 am     Reply with quote

PIC18F24Q10.

.................... setup_timer_5(T5_INTERNAL | T5_DIV_BY_1 | T5_GATE);
0AEE: MOVLW 01
0AF0: MOVWF T5CLK // correct
0AF2: MOVLW 07
0AF4: MOVWF T5CON // correct, but bit 2 (/SYNC) has no effect with this clock source
0AF6: MOVLW 80
0AF8: MOVWF T5GCON // incorrect; the polarity bit (bit 6) is wrong
0AFA: CLRF T5GATE

From the device’s header file:
#define T5_GATE 0x8000
#define T5_GATE_INVERTED 0xC000

^ Those two defines are reversed. The same error extends to all odd timers (T1, T3, and T5).

I've alerted CCS about this issue.
newguy



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PostPosted: Wed Oct 18, 2023 1:31 pm     Reply with quote

Heard back from CCS.

Quote:
It seems this has always been the way we have done this. Not sure it if was an initial error or if the documentation for the old chips was wored differently.

At this point we don't think we should change it because it could impact users code. We will add a note near the definitions to clarify the operation.
Ttelmah



Joined: 11 Mar 2010
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PostPosted: Thu Oct 19, 2023 7:39 am     Reply with quote

It is very interesting. If you look at the logic diagram for the timers, the
gate signal is fed through an XOR gate. The control bit is shown as being
inverted and fed into the other input of this. Now on an XOR, a 1 on the second input would invert the output.
So 0 is actually inverting, and 1 turns this off!.

The timer must then use -ve logic for the clock itself. However the diagram
shows it using a rising edge.

So the diagram disagrees with the stated levels in the register data,

Whimper.
It may well have been documented with the wrong edges on the very
first data sheet for the chip, given the diagram.... Sad
newguy



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PostPosted: Thu Oct 19, 2023 8:14 am     Reply with quote

I actually found that quite some time ago but I never bothered to report it. With the #use spi() baud rate issue I already reported earlier this week, I thought why not?

I can confirm that 0x80 causes the timer to count when the external gate signal is low, but I must admit I didn't catch the detail in the block diagram that you have. Microchip has another clarification to add to that processor's errata it seems.

It's fair them not wanting to fix the #defines but I did ask them to put a note in the help file, as that's always my first coding stop. Help -> header -> disassembly when things don't go right -> data sheet. With the note in both the help and the header file it's going to be more difficult to miss.
Ttelmah



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PostPosted: Thu Oct 19, 2023 11:20 am     Reply with quote

I'd also comment, that historically this was the sort of thing CCS used
to put in their readme. Recently they haven't updated this for several
compilers. They really ought to be making a point of doing this.

Discrepancies between the internal circuits and the register values
are fairly common now on the Microchip data sheets. In the early
PIC days, their sheets were great. This is no longer the case. Sad
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