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Purging UART data in the receive buffer
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temtronic



Joined: 01 Jul 2010
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PostPosted: Sun Apr 24, 2022 6:30 am     Reply with quote

You should also consider a 'timed UART receive'. CCS shows a sample in the Q&A section of the manual.
You need to calculate how long a 'good' receive will take ( say 10ms). You then preload a timer for 20ms ( double the expected time to get the data..).
The 'timed serial ISR' will either finish(return) when either all data is received OR the 'timeout' occours. Using this technique means the program will not 'hang' in the serial ISR.
kgng97ccs



Joined: 02 Apr 2022
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PostPosted: Mon Apr 25, 2022 7:59 pm     Reply with quote

Thank you, Temtronic, for your suggestion. Are you referring to page 334 of the November 2021 manual?
kgng97ccs



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PostPosted: Mon Jun 20, 2022 11:56 pm     Reply with quote

I gathered from the forum posts that it is generally best to stay in an ISR for as short a time as possible, so that the MCU can attend to other tasks if needed.

However, if I expect to receive a stream of bytes of data (say 200 of them) from a UART, and wish to ensure minimal chance of the data getting missed or corrupted because the MCU attends to other interrupts while receiving the data, would it make sense to complete reading all the bytes within the ISR (for #int_rda, for example) when the first UART interrupt occurs, instead of reading one byte per interrupt?

I will appreciate any comments or suggestions. Thank you.
Ttelmah



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PostPosted: Tue Jun 21, 2022 12:20 am     Reply with quote

Generally, UART data is so slow that it is not worth worrying about this.
Understand that a UART character takes 10 bit times (or more), so even
at 115200bps, this is 87uSec, on a chip at (say) 16MHz, this is 350
instructions, so i is very rare for a second character to have arrived by
the time you are leaving the interrupt.
The exception is with chips that have much larger receive buffers (so the
DsPIC's for example), and/or when using very high baud rates:
Code:

#INT_RDA
void character_rx(void)
{
   int t;
   do
   {
      buffer[next_in]=getc();
      t=next_in;
      if (++next_in >=BUFFER_SIZE)
          next_in=0;    //wrap the buffer size
      if(next_in==next_out)
         next_in=t;      // Buffer full !!   
   } (while kbhit());  // loop if another character has arrived.
}


This shows how to efficiently have the receive 'loop' if another character
has arrived before the exit. Also how to correctly handle the buffer size
wrapping (this copes with buffer sizes that are not 'binary' sizes, the
supplied example file has problems if these are used).
kgng97ccs



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PostPosted: Tue Jun 21, 2022 9:15 pm     Reply with quote

Thank you, Ttelmah, for helping me see the UART data transmission time in perspective.

1. If, due to some delay in servicing a UART interrupt, there is more than one byte of data in the receive buffer at the time the corresponding UART ISR is called, but the ISR reads only one byte and then exits, will another UART interrupt (caused by the presence of data in the receive buffer) be triggered immediately after the ISR exits?
2. If no, would it be appropriate in general to do a similar do-while loop to read all characters in the receive buffer whenever a UART ISR is called, in case there is more than one character in the receive buffer?
Ttelmah



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PostPosted: Tue Jun 21, 2022 11:19 pm     Reply with quote

Understand that the standard PIC only has one actual buffer character.
Has the incoming shift register, and one buffer. So 1.9999 characters max.
Now the only occassion where kbhit will test true is when the final bit
at the end of the character arrives between the moment the character
is read, and the test. Almost impossible.
With normal handling the ISR should have been left hundreds of instructions
before the next character arrives.
Yes, if there is another character to read, the ISR will just be called again.
kgng97ccs



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PostPosted: Wed Jun 22, 2022 12:41 am     Reply with quote

Thank you, Ttelmah. Hope you do not mind that I continue to pursue this enquiry.

For the PIC18LF46K22, the datasheet says “The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver” (Section 16.1.2). In other places, it says “two-character input buffer” (Section 16.0) and “The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed” (Section 16.1.2.6).

So, is it correct that for the PIC18LF46K22, it is possible to have two complete characters in the receive buffer waiting to be read?
Ttelmah



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PostPosted: Wed Jun 22, 2022 3:43 am     Reply with quote

This is one of the differences between the USART (most chips), and the
EUSART. However the timing remains the same. Even working at 115200bps
if all your ISR's are kept short (so the INT_RDA cannot be left 'unserviced'
because the processor is stuck in another interrupt), you should never see
another character arrive while still handling the first.
I've used RS485 serial links at 1Mbps, and have never seen a second
character arrive and be available before leaving the ISR.
The exception would be if you had an ISR for something else, that took
more than a character time to be serviced. In this situation, unless using
hardware priorities, you have the potential for a second character to
arrive before the ISR is serviced, if the processor is busy servicing the other
interrupt, when the first character arrives.
Key point is that the RDA interrupt flag cannot actually be cleared until the
FIFO is empty. Hence the interrupt will just be called immediately again
if a second character is available.
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