I2C - detecting when a Slave read is bad via CCS functions?

[allenhuffman]

I have a situation on a 24FJ64GA002 acting as an I2C slave.

The Master begins writing a message, and the analyzer shows the first byte is ACKd by the PIC. All the following data bytes are NAKd. The host, using FTDI drivers that don't return errors, then goes to READ from the PIC. I see the WRITE (address + read) is ACKd by the PIC.

My code needs to be able to detect this situation. My ISR is called for the first byte of the WRITE (address). I set a flag and turn on an LED on my hardware.

Then it is as if I don't get anything else until the master does the READ (write address + read bit). I see a separate flag gets set indicating that READ ISR was hit... Then nothing because I am using clock stretching and my code has never processed a message to have a response ready ;-)

i2c_read() only returns data, so I get the address (which is ACKd). I'm not sure how to tell what happened in the chip for the rest of the bytes.

The I2CxSTAT register had ACK/NAK status but "Do not check the state of ACKSTAT when receiving data"

I'm already looking for a STOP bit, which the PIC apparently doesn't see in this case (it's in the capture). From my LED status and flags, I know I saw the Master WRITE (addr ACK), and I can tell the PIC saw the master READ (addr ACK).

Any tips on how I can detect that the PIC is NAKing stuff?
_________________
Allen C. Huffman, Sub-Etha Software (est. 1990) http://www.subethasoftware.com
Embedded C, Arduino, MSP430, ESP8266/32, BASIC Stamp and PIC24 programmer.
http://www.whywouldyouwanttodothat.com ?

[Ttelmah]

What you seem to be describing is where I2C_ISR_STATE==0x80.
On this the slave has to read the address byte, and pre-load the reply
for the following master read. Both things have to happen, or as you say
the bus will get locked. If your slave has not got a reply ready, then it
needs to reply with some form of 'NULL' data to say it is not ready.

[allenhuffman]

0x80 is seen, then the PIC starts NAKing the subsequent bytes from the Master. That is what I am trying to detect.

My new code always answers the read request from the Master (same way the example CCS code does, enabling clock stretch) but since my code has never seen a request from the Master write, it will never reply. We want/need clock stretching since it may take a few ms to get a reply ready between Master write and Master read.

My current approach is to just time out and release the clock. However, it would be nice to actually detect the problem instead of waiting for a timeout.
_________________
Allen C. Huffman, Sub-Etha Software (est. 1990) http://www.subethasoftware.com
Embedded C, Arduino, MSP430, ESP8266/32, BASIC Stamp and PIC24 programmer.
http://www.whywouldyouwanttodothat.com ?

[Ttelmah]

There should not be any 'bytes from the master' after 0x80. 0x80 is
saying the bus is to be reversed for a master read. In this mode the slave
can only send and the master read.