| View previous topic :: View next topic |
| Author |
Message |
JosedeJesusC
Joined: 29 Mar 2013
Posts: 24
|
| Count clock cycles of the PWM |
 Posted: Thu May 09, 2013 2:19 pm |
 |
|
Hi everyone!!!
I have a doubt. how can I count 13 clock cycles from pwm?
The PWM generate a signal to synchronize an external ADC. but when the data is ready I need count 13 cycles before to read it, I wonder the
function setup_timer_2() may be useful but I don't know if there something else to do
I hope that someone can help me !!!
 |
|
 |
asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
|
|
| Posted: Thu May 09, 2013 2:28 pm |
|
|
a better place to start is by telling WHAT ADC you want to control??
and showing the code you would use to go about the task
you indicate.
as you frame this question, you have added the odd constraint of using the PWM module as a clocked one-shot , a task it is ill suited for. |
|
|
alan
Joined: 12 Nov 2012
Posts: 357
Location: South Africa
|
|
| Posted: Thu May 09, 2013 2:31 pm |
|
|
| It sounds more that he wants SPI as some of the external ADC actually does the conversion as you CLK the data out and needs 13 cycles before 1st bit is valid like MCP3202 |
|
|
JosedeJesusC
Joined: 29 Mar 2013
Posts: 24
|
|
| Posted: Thu May 09, 2013 6:29 pm |
|
|
The ADC is ADS1254 who needs a external clock signal.
The pwm from pic18f4550 generates the clock signal. I'm going to use SPI communication to receive the data, but as the data sheet says I need to wait 13 clock cycles before to receive it.
The problem is that ADC uses the same pin DOUT/DRDY to indicate the data is ready, after 13 clock cycles, send the data.
I just have a code to configure the PWM, as you know it's simple.
But if you want this the code :
How can I count the cycles before to read the data from the ads1254?
| Code: |
#include<18F4550.h>
#fuses HSPLL, NOWDT, NOPROTECT, NOLVP, USBDIV, PLL1, CPUDIV1, VREGEN, MCLR
#USE delay(clock = 48000000)
#define USB_HID_DEVICE FALSE
#define USB_EP1_TX_ENABLE USB_ENABLE_BULK
#define USB_EP1_RX_ENABLE USB_ENABLE_BULK
#define USB_EP1_TX_SIZE 8
#define USB_EP1_RX_SIZE 8
//#define PWM_FREQUENCY dato[0];
//#define LEDS_OUTPUT dato[1];
#include<pic18_usb.h>
#include<picUSB.h>
#include<usb.c>
#BYTE TRISA = 0X0F92
#BYTE PORTA = 0X0F80
#BYTE TRISC = 0X0F94
void setting(void)
{
usb_init();
usb_task();
usb_wait_for_enumeration();
TRISA = 0X00;
TRISC = 0X00;
output_low(PIN_C2);
setup_ccp1(CCP_PWM);
}
void set_pwm(int *F)
{
setup_timer_2(T2_DIV_BY_16, F[0], 1);
set_pwm1_duty(f[0]/2);
}
void main(void)
{
unsigned int dato[8];
unsigned int envia[8];
envia[0] = 0;
setting();
while(1)
{
if(usb_enumerated())
{
if(usb_kbhit(1))
{
usb_get_packet(1, dato, 8);
set_pwm(dato);
PORTA = dato[1];
envia[0]++;
usb_put_packet(1, envia, 1, USB_DTS_TOGGLE);
}// end usb kbhit
}// end if usb enumerated
}
}
|
This code is just a way to test the pwm frequency, watching the oscilloscope the pwm makes the frequencies what I need with a good accuracy. |
|
|
asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
|
|
| Posted: Fri May 10, 2013 8:22 am |
|
|
if you are really happy with the clock frequency you generate by PWM,
then so be it. I would NOT supply the clock to the ADC chip as you have chosen.
as to the ADC driver- i have used that part via bit banging -
NOT with CCS/PIC SPI hardware.
note: that to read the state of the DO pin - you need a weak pullup resistor to Vdd - so let figure 12 and 14 of the datasheet be your guide - as COUNTING clocks is not required really. be sure to allow minimumm settling time when you change ADC mux inputs!!
best-o-luck |
|
|
JosedeJesusC
Joined: 29 Mar 2013
Posts: 24
|
|
| Posted: Fri May 10, 2013 12:07 pm |
|
|
Thanks for your reply asmboy!!
As I understood It's not necessary, a continuous clock it's not necessary when I need read from the ADC an analog signal then I generate the clock , but if I wanna read continuously, the goal is read data from a load cell
so the tests need long time.
about the bit banging, I can generate the clock signal via software, instead the PWM.
that resistance that you said I have to connect from the pin DO to VDD of the ads1254 isn't it right?.
I'm confused so I hope you can help me
thanks best regards |
|
|
asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
|
|
| Posted: Fri May 10, 2013 1:36 pm |
|
|
| Quote: |
generate the clock
|
with 48mhz as the use delay - and an external freq source for the pic - it implies you have 12 MHz available.
if you are using a crystal or oscillator for the pic - that
would be a better source , even if divided down further by some 74HCT logic flipflops.
what does the data sheet for the ADC say about it ???
both software and pwm are poor choices for clocking the ADC IMHO. |
|
|
JosedeJesusC
Joined: 29 Mar 2013
Posts: 24
|
|
| Posted: Wed May 15, 2013 10:32 am |
|
|
Hi asmboy thanks for your reply!!!
first I owe you an apology because I didn't know explain my doubt.
But looking for information I've found an application report from Texas instruments.
the PWM doesn't synchronize the ADS1254 to pic, instead that, the PWM source the clock (MCLK) for the delta sigma modulator to set the data output rate and the cut off frequency of the sync filter.
the link to the article it's below:
http://www.ti.com/analog/docs/litabsmultiplefilelist.tsp?literatureNumber=slaa242&docCategoryId=1&familyId=2019
this document says, that, for synchronize the ADS1254 and get the data result, I can use the SPI in this particular application and for the microcontroller MSP430F49
I just take the concept to create a driver for to the ADC with the pic18f4550.
to reset the device I need hold high the SCLK of the SPI!!!! for 4*(384 MCLK) then prepare the ADC for data transfer.
to power down the device I need hold high the SCLK by 20*(384MCLK)
to avoid more confusion the MCLK should be PWM, and the SCLK should be the SPI CLK.
how Can I do this? !!!! hold high the SCLK to reset the device only for this time, and power down it
thanks best wishes asmboy I hope that you can help me |
|
|
asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
|
|
| Posted: Wed May 15, 2013 11:01 am |
|
|
the max system clock for the ADC is 8 MHz.
you can clock slower, but conversion times will be longer.
thats why PWM is a poor choice for it.
anyway, it is independent of the SPI clock!!!
all the critical timings and counts are related to the SPI clock,
no reason to count system convert clock -
as the values you are obsessing over are informational and not required to make a good driver at all.
Learn to count on the Dout "data ready" function if you use the weak pull up resistor on that port that i suggested.
EVERYTHING you need to know is in Figure 12,13,14 and 15.
the relation of SCLK to Dout is the only one you need to consider, once you understand the part better.
ONE other thing that is not obvious:
on EARLY SILICON versions of the part---
every time you change input selection - take a dummy reading to throw away. as changing input mux is not guaranteed to flush the last convert register reading. this applies to many other parts in the same family.
it is believed fixed in current production.
-----------
you make this much harder than it needs to be |
|
|
JosedeJesusC
Joined: 29 Mar 2013
Posts: 24
|
|
| Posted: Wed May 15, 2013 1:03 pm |
|
|
thanks for your reply asmboy.
Ok I'm going to forgive the PWM and count MCLK cycles.
The key is on the function DOUT/DRDY.
About that pull up resistance all I have to do is connect it, from Dout to VDD
to accommodate the CMOS output to TTL input.
do you think what 640 Ohms is a good value?
I'm using a 4 MHz crystal to the USB module
can the crystal be interfaced to CMOS input of the ADS1254 with that 74HCT flip flop? |
|
|
PCM programmer
Joined: 06 Sep 2003
Posts: 21708
|
|
| Posted: Wed May 15, 2013 2:21 pm |
|
|
Jose,
I have a question that no has asked. You want a driver for the ADS1254
which is a 24-bit ADC. I don't know what signal you want to measure
but let's assume it's a 0v to 5v signal. 24 bits is 2^24 = 16777216.
So your resolution would be 5v / 16777216 = 0.000000298 volts.
Each ADC lsb is 298 nano-volts.
Why do you need this resolution ? What device are you measuring ?
Do you believe that you can design the analog section of your board
to keep the noise level down to a nano-volt level ? The average noise
in the digital section of a board will be at least 20 mv. How do you
propose to keep that noise out of your analog section ?
So my basic questions are, do you really need nano-volt resolution and
can you even make a circuit to allow it to work ?
Because, if you don't really need this 24-bit ADC chip, there are chips
with a lower number of bits that cost less and are much easier to write
a driver for. |
|
|
asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
|
|
| Posted: Wed May 15, 2013 2:33 pm |
|
|
| Quote: |
do you think what 640 Ohms is a good value?
|
a weak pullup is fine - this is CMOS - so 22k ohms is fine.
640 ohms is FAR too much load to be useful.
don't go there !!!
BTW: PCM_P raises an excellent point.
Every aspect of even a 16bit clean conversion requires good analog circuit design skills, which I admit i take for granted.
I have been designing analog and RF circuits for several decades before i ever did my first pic assembler program ( for a 16c62) and never think to question the requisite design skills that low noise conversion requires.
PCM_P is certainly correct, as if the circuit is not exquisitely well done, analog wise, forget 24 or even 16 good bits.
You could get get a 12 bit resolution PIC and make the best of it.
and save a bundle too. |
|
|
JosedeJesusC
Joined: 29 Mar 2013
Posts: 24
|
|
| Posted: Thu May 16, 2013 11:46 am |
|
|
Hi asmboy and PCM Programmer !!!! I'm sorry If I don't Know many things, but I'll keep trying to learn more.
The data sheet says that ADC gives 19 free noise resolution bits, achieving more resolution it's important to get better information of iron samples under fatigue cycles, or simple stress tests (stretch or compress).
The filtering of signal will be in LabVIEW to achieve more free noise resolution, we've been calculating the elliptical filter constants with matlab. The LabVIEW 2007 embedded has especial functions to develop our own filters.
The Sensor is a load cell made of strain gauges in a full Wheatstone bridge, the behavior is linear.
The load cell has internal circuit to avoid common rejection noise, and the internal impedance of the lines.
I'm going to use an instrumentation amplifier to get the signal, all this it's not enough, but with free noise resolution of 19 bits it's a good beginning. |
|
|
asmboy
Joined: 20 Nov 2007
Posts: 2128
Location: albany ny
|
|
| Posted: Thu May 16, 2013 1:13 pm |
|
|
have you evaluated your load cell amplifier design for
dynamic range and low noise ?
if you are trying to sample a narrow window of delta-strain , within a large
voltage swing range, consider adding circuitry offering clipping, precise DC T-comped offsets, and more analog window gain, as that ought to provide better results than trying for 19 bits of meaning from a 1/10th of a volt of delta-S - BTDT with eddy current sensors that had too little deviation for happy A/D resolution.
and while the output of an I-amp is an excellent way to drive the input of
your A/D
-the connection methods and shielding of your analog circuitry -
PLUS careful star-grounding are still essential to get even 15 good bits.
it remains true that careful design and testing of your
analog circuitry is an essential aspect. |
|
|
JosedeJesusC
Joined: 29 Mar 2013
Posts: 24
|
|
| Posted: Fri Jul 26, 2013 10:54 am |
|
|
Hi asmboy.
yeah I've got the information above the load cell. It's got circuits to avoid noise, the amplifier's going to be designed with a monolithic of ANALOG DEVICE.
About the ADC I have the CLK with the CD40106BE, and HEF4013BP, to have 3 frequencies and set the filter.
A decoupling capacitor of 10pF between Analog Vdd and Analog GND and another between Digital Vdd and Digital GND.
but the result is in offset two's complement, I need to conditioning the value? how? |
|
|
|
FAQ 
Search
Register
Profile 
Log in to check your private messages 
Log in
