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Message |
gil.fonea@sds-tech.com
Joined: 24 Mar 2010
Posts: 24
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| Unexpected second ext2 interrupt |
 Posted: Wed Nov 24, 2010 2:13 am |
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Hi,
I am using 18F85J90 with CCS version 4.073.
One of the functions is receiving interrupt from gpio device.
| Code: |
void main()
{
setup_timer_0(RTCC_INTERNAL | RTCC_DIV_16);
setup_timer_1(T1_DIV_BY_1 | T1_INTERNAL);
enable_interrupts (INT_SSP);
enable_interrupts (INT_RB);
enable_interrupts (INT_EXT);
enable_interrupts (INT_EXT3);
enable_interrupts (INT_EXT2);
enable_interrupts (INT_EXT1);
ext_int_edge(0, H_TO_L);
ext1_interrupt();
ext_int_edge(2, H_TO_L);
ext_int_edge(3, H_TO_L);
// timer interrupts ...
enable_interrupts (INT_TIMER0);
enable_interrupts (INT_TIMER1);
// global int ...
enable_interrupts (GLOBAL);
delay_ms(50);
DisplayFirmwareVersions();
LcdDisplayNormal();
UpdateLowBatDisplay();
while(1)
{
...
if (event_flag)
{
integrator_event_flag = 0;
parse_gpio_request();
SetupMenuTimer(MENU_TIMER_2_SEC); //enable more timeout
}
...
}
}
void parse_gpio_request()
{
byte dummy_read=0;
byte io_register;
byte io_changed = 0;
clear_interrupt(INT_EXT2);
}
#INT_EXT2
void ext2_interrupt()
{
setup_oscillator(OSC_8MHZ);
output_high(PIN_F2); // debug
delay_ms(DEBOUNCE_TIME_MS);
event_flag = 1;
output_low(PIN_F2); // debug
}
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The gpio interrupt output is connected to ext2 interrupt input in the 18F85J90.
When gpio device outputs a negedge, the controller receives an interrupt, sets the event_flag=1 and execute parse_gpio_request() in main loop.
The phenomena i see is that for a single negedge #INT_EXT2 pops twice: once when negedge and again before parse_gpio_request() is executed.
I cannot understand where does the second interrupt comes from, any ideas?
Regards,
_________________
Gil F. |
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Ttelmah
Joined: 11 Mar 2010
Posts: 19375
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| Posted: Wed Nov 24, 2010 3:22 am |
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First comment. Sort out your setup. You should _not_ change the interrupt edge after enabling the interrupt. This can give a spurious trigger.
Sequence should be:
Set interrupt edge
clear interrupt
enable interrupt
Are you using the internal voltage regulator?. If not, have you got the VddCore pin tied to Vdd, with a well decoupled short track?. If you are, are you sure your decoupling capacitor meets the ESR requirements. These chips are quite fussy about this area.....
You need to look very carefully at the ground between the GPIO device, and the PIC, and triple check that the input is not actually receiving noise to trigger a second interrupt.
The interrupt is already cleared by the interrupt handler. Are you sure that your delays are just not adding up to more than the time between packets?. You have a delay in the interrupt (research why this may not be a good idea.....), and delays in your external code (makes this an even worse idea....).
Best Wishes |
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gil.fonea@sds-tech.com
Joined: 24 Mar 2010
Posts: 24
|
| Unexpected second ext2 interrupt |
| Posted: Wed Nov 24, 2010 3:42 am |
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Thanks for reply.
You sent me some real good tips.
Moreover, I have found the problem.
Half of the gpio device ports are output to outer world and half are inputs from outer world.
Somewhere in main loop the outputs to outer world are configured by the pic (using i2c). This caused a loop-back interrupt on ext2.
Regards
_________________
Gil F. |
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