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jecottrell
Joined: 16 Jan 2005 Posts: 559 Location: Tucson, AZ
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"Could Not Start Target" |
Posted: Fri Dec 23, 2005 1:55 am |
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Brand new to ICD-U. I believe I've got all my bases covered. I get a warning when trying to debug:
Code: | Could not start target: The target was not halted after reset Check the target oscillator and MCLR. |
Vdd on PIC is at 3.3v, MCLR is at 4.04v, oscillator isn't starting. However, ICD programs the part fine in non-debug mode.
FLASH!
Just before hitting submit I had a bright idea. I looked at my fuses and saw that I had PUT enabled. Disabled it and now it's working.... Go figure. |
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Guest Guest
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Could not start target |
Posted: Thu Jan 12, 2006 4:22 am |
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I have the very same problem - but specifying NOPUT did not help.
I use ICD-U40 with a PIC16F76. The uP is powered with 5V. My program is simple: It writes a start message to the UART and to the debugger and then enters a loop where it periodically sends a character to the UART - about once every 5 s.
When invoking the debugger from PCW-IDE, the ICD connects, the program is loaded and then the silly error message comes up. But the program runs, as I can see from its output to the UART. But no debugging is possible (red bar saying: "not ready") and no debugger-output is visible in the Monitor window.
Does anyone have good advice? |
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James Guest
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Could not start target |
Posted: Sat Jan 14, 2006 12:52 pm |
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I have the same problem and I have tried many fuse combinations and replaced my power supply, oscillator, resister, capacitors, and event my PIC18F6627, but just can't invoke debugger. Maybe it is time to replace the ICD and the compiler.
Here is what CCS tech support told me. It might work for you.
There are some reasons causing the debugger reset error, bad target clock(programming doesn't use the target clock, but debugging does), bad clock fuse or any other fuse(clock fuse doesn't match the target clock or some other fuse cannot be used in the debug mode), bad connection (make sure MCLR, CLK, data, VDD and VSS are connected firmly and there is no other circuitry on CLK and data and 47K pull up on MCLR(no capacitor), debugger more sensitive to these that programming bad target VDD(make sure there is no noise on VDD) |
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rklosinski Guest
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Posted: Thu Mar 02, 2006 9:38 pm |
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I spent 2 days with this problem! I changed POT to NOPOT, and it works!!! Thanks |
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