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maximum clock frequency

 
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tmach



Joined: 20 Dec 2003
Posts: 14

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maximum clock frequency
PostPosted: Sat Dec 20, 2003 2:20 pm     Reply with quote
hello!
I have implemented software SPI to read in 64 bits of data using shift right and shift left functions. I am using PIC16F874A and 20Mhz osc configured as HS.
I am wondering what could be the maximum clock frequency at which I could send data to the PIC!

Thanks.
mach
Ttelmah
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Re: maximum clock frequency
PostPosted: Sun Dec 21, 2003 5:33 am     Reply with quote
tmach wrote:
hello!
I have implemented software SPI to read in 64 bits of data using shift right and shift left functions. I am using PIC16F874A and 20Mhz osc configured as HS.
I am wondering what could be the maximum clock frequency at which I could send data to the PIC!

Thanks.
mach

There isn't really an answer.
The problems are not with the clock frequency itself, but other factors (such as the gap between characters). I use a SPI bus to send data between two PICs, and run it basically 'flat out' (FOSC/4). However after the first 'trigger' character, the transmitter has to pause long enough, to ensure that the receiving chip has seen this character, and is ready to accept the rest of the data block. The time needed for this can be suprisingly long (especially if the chip has other interrupt handlers). You need to work out the worst case latency to respond to a character (remembering that the handler must load the next 'return' character, before the system starts clocking the second byte), and will need to pause for this long in the transmitting system. Once this is done, the response for individual characters (assuming the code now goes into a dedicated 'receive' routine, and does not use interrupts to handle the latter bytes), can be only a matter of a uSec or so between characters.

Best Wishes
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