ADC on dsPIC33CK1024

[nazoa]

Hello
I am trying to use the ADC on a dspic33Ck1024MP710 chip.
I am using version 5.118 of the PCWHD compiler.

So, I setup the ADC as follows:

setup_adc_ports(sAN1|sAN11|sAN12|sAN13|sAN15, VSS_VDD);
setup_adc(ADC_CLOCK_SYSTEM|ADC_CLOCK_DIV_32);

Then, to make a reading I use the following:

set_adc_channel(13);
delay_us(10);
R=read_adc();

The result is that the code locks up on read_adc().
It's as if the ADC is not on or being clocked so the code waits for ever for the conversion.

Any suggestions?

Many thanks.

[nazoa]

Hello
The ADC functions in the CCS compiler didn't work for the dspic33ck1024 chip in my case. But I have had success writing to the various ADC control registers directly. I got a lot of help from the Microchip forum (thanks Miguel Rodrigues for your post). Anyway, in case anyone else is interested here is the code that works (shared core and core 1) in my case.

// ***************************************************
// ** Configure shared ADC module in dispc33ck chip **
// ***************************************************
void config_shared_adc(uint8_t resolution, uint8_t adc_channel)
{
unsigned int16 A;
#word ADCON1L = 0xB00 // ADC control registers [33ck chip]
#word ADCON1H = 0xB02
#word ADCON2L = 0xB04
#word ADCON2H = 0xB06
#word ADCON3L = 0xB08
#word ADCON3H = 0xB0A
#word ADCON5L = 0xC00
#word ADCON5H = 0xC02

ADCON1L = 0x00; //Disable ADC module before setting up

switch (resolution)
{
case 12:
{
bit_set(ADCON1H,6);
bit_set(ADCON1H,5);
break;
}
case 10:
{
bit_set(ADCON1H,6);
bit_clear(ADCON1H,5);
break;
}
case 8:
{
bit_clear(ADCON1H,6);
bit_set(ADCON1H,5);
break;
}
}


ADCON2L = 0x0003;
ADCON2H = 0x0030;

ADCON3L = 0x0000; // AVDD/AVSS as references
ADCON3H = 0x0000; // Clock = Fosc /2.

ADCON5L = 0x0000;
ADCON5H = 0x0F00;

bit_set(ADCON3H,7); // Enable Shared core
bit_set(ADCON5L,7); //Powerup

ADCON1L = 0x8000; //Enable module

Do
{
A=ADCON5L;

}
while(bit_test(A,15) == 0); //wait for shared core ready flag
}

//*******************************
//** Setup dedicated adc core1 **
//*******************************
void config_dedicated_adc1(uint8_t resolution)
{
unsigned int16 A;
#word ADCON1L = 0xB00 // ADCON1L control register [33ck chip]
#word ADCORE1L = 0xBD8
#word ADCORE1H = 0xBDA
#word ADCON3L = 0xB08 //ADCON3L control registr [33ck chip]
#word ADCON3H = 0xB0A
#word ADCON4H = 0xB0E
#word ADCON5L = 0xC00
#word ADCON5H = 0xC02

bit_clear(ADCON1L,15);

ADCORE1L = 0x0030;
ADCORE1H = 0x0000;

switch (resolution)
{
case 12:
{
bit_set(ADCORE1H,9);
bit_set(ADCORE1H,8);
break;
}
case 10:
{
bit_set(ADCORE1H,9);
bit_clear(ADCORE1H,8);
break;
}
case 8:
{
bit_clear(ADCORE1H,9);
bit_set(ADCORE1H,8);
break;
}
}

ADCORE1H = ADCORE1H | 0x0010; //4 clock periods

ADCON3H = 0x0000; // frequency = Fosc /2.

ADCON4H = 0x04; // Using ANA1 PORT

bit_set(ADCON3H,1); // Enable ADC Core1
bit_set(ADCON5L,1); // Power up

bit_set(ADCON1L,15);

Do
{
A=ADCON5L;

}
while(bit_test(A,9) == 0); // wait for C1RDY - ready flag

}

//**************************
//** Getting the ADC data **
//**************************
unsigned int16 get_ADCdata (uint8_t adc_channel)
{
#word ADCBUF0 = 0xC0C

unsigned int16 data = 0;
unsigned int16 A;

volatile uint16_t* pResultBuffer = (&ADCBUF0) + adc_channel;

// Select the channel of interest
A=ADCON3L;
A=A & 0xFFC0;
A=A | adc_channel;
ADCON3L=A;

bit_set(ADCON3L, 8); //Issue a trigger
delay_us(20);

// Store data from the buffer in the predefined data variable.
data = (*pResultBuffer);

return data; // data from ADC.

}

[Ttelmah]

I think you should ask CCS to add an example for using this ADC.

If you look, the big problem was that you were not setting up the clock
for the shared core. The compiler has separate defines for this, but
doesn't explain these anywhere.

I managed to generate setups that gave he same result as your later
code, by playing with the CCS options, but the lack of documentation
makes this an almost impossible task.

[nazoa]

Yes, I have asked CCS sometime ago about this issue. Waiting for their reply.
You may well be right as the original code was freezing when querying the shared core adc.