I2C slave reactions to SDA+SCL locked low by master

[bdeb]

CCS 5.075 MPLAB-X 5.15 PIC16F18346 @3.0V

Dear gurus,

Sorry to take your time, since this may well be a Microchip hardware question. I'm making (yet another) I2C slave connected to a GSM module.
PIC controls GSM on/off - but GSM is I2C master when active.

Problem is that this GSM module locks SDA+SCL low when off. I get fair warning before turning off, but I don't know what action to take!

PIC data sheets and NXP UM10204 give me no clues to this condition. What have I missed?

At the moment I do nothing and have no problems or "false" SSP interrupts, but even that feels scary..

Considered optional bus isolators/drivers, but most are dust-size BGA and have no quiescent current specified. (PIC + sensors <40uA)
Taking the easy way out and asking you first!



All the best:

/Björn

[Ttelmah]

This is perfectly reasonable.

Point is that I2C 'start', is triggered by dropping the SDA line, while SCL
is high. With both lines held low, this can't happen (provided the hardware
ensures that SCL drops with or before SDA).
So your chip can never see a 'start'. The I2C hardware won't trigger a byte
receive, or a stop etc., till a start has been seen, hence no false SSP
interrupts.

If you want to be really careful, the obvious thing would be when the 'off'
triggers, simply disable the I2C peripheral.

Set up your I2C, with the 'NOINIT' option.
Then at the start of your code call i2c_init(streamname, TRUE); to initialise
the I2C.
Then when the master is going to stop, call i2c_init(streamname, FALSE);
to turn off the I2C peripheral. When you want to listen again, use the
TRUE syntax to turn the I2C back on.

[bdeb]

Thank you Ttelmah,

Yes, I want to be extra careful here - will do as you suggest.

All the best:

/Björn