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mvanvliet
Joined: 02 Jun 2009
Posts: 123
Location: The Netherlands
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| Microchip Class B IEC60730 code implementation in CCS |
 Posted: Fri Jan 24, 2020 9:37 am |
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I'm trying to implement the Class B (IEC60730) files into a CCS program, I've eliminated most errors, but there are a few left which I can't solve. One of them is:
| Code: |
/**********************************************************************
* © 2013 - 2014 Microchip Technology Inc.
*
* Project Name: Class B Library
* FileName: CLASSB_ClockTest.c
* Dependencies: CLASSB_ClockTest.h
* Processor: PIC16F1xxx
* Compiler: XC8
* IDE: MPLAB® IDE or MPLAB® X
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Description: This file contains functions to check the MCU clock
* source.
*
**************************************************************************
* MICROCHIP SOFTWARE NOTICE AND DISCLAIMER: You may use this software, and
* any derivatives created by any person or entity by or on your behalf,
* exclusively with Microchip's products in accordance with applicable
* software license terms and conditions, a copy of which is provided for
* your referencein accompanying documentation. Microchip and its licensors
* retain all ownership and intellectual property rights in the
* accompanying software and in all derivatives hereto.
*
* This software and any accompanying information is for suggestion only.
* It does not modify Microchip's standard warranty for its products. You
* agree that you are solely responsible for testing the software and
* determining its suitability. Microchip has no obligation to modify,
* test, certify, or support the software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED
* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
* PARTICULAR PURPOSE APPLY TO THIS SOFTWARE, ITS INTERACTION WITH
* MICROCHIP'S PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY
* APPLICATION.
*
* IN NO EVENT, WILL MICROCHIP BE LIABLE, WHETHER IN CONTRACT, WARRANTY,
* TORT (INCLUDING NEGLIGENCE OR BREACH OF STATUTORY DUTY), STRICT
* LIABILITY, INDEMNITY, CONTRIBUTION, OR OTHERWISE, FOR ANY INDIRECT,
* SPECIAL, PUNITIVE, EXEMPLARY, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE,
* FOR COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE,
* HOWSOEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY
* OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWABLE BY LAW,
* MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS
* SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID
* DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF
* THESE TERMS.
*************************************************************************
*
* REVISION HISTORY:
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Author Date Comments on this revision
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* CT 09/15/2008 First release of source file
* Mike Cahill 11/11/2010 Updated for HI-TECH v9.80
* MVL 02/22/2011 Modified for HI-TECH v9.81
* Corey Simoncic 03/25/2013 Updated for XC-8 PRO v1.12
* Willem J Smit 10/20/2014 RamMarchBTest and RamCheckerBoardTest update
*
* Version 3.01
*
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* ADDITIONAL NOTES:
*
**********************************************************************/
#include "CLASSB_ClockTest.h"
uint16_t CLASSB_timerCount = 0;
uint16_t CLASSB_Clockcount = 0;
uint8_t CLASSB_TRISC_temp;
uint8_t CLASSB_INTCON_temp;
uint8_t CLASSB_T1CON_temp;
uint8_t CLASSB_PIE1_temp;
/******************************************************************************
* Description:
* The Clock test implements the independent time slot monitoring H.2.18.10.4
* defined by the IEC 60730 standard. It verifies the reliability of the system
* clock (i.e., the system clock should be neither too fast nor too slow)
*
* Input:
* clockFrequency - system clock frequency.
* referenceFrequency - reference clock frequency.
* msec - the time in milliseconds to run the test.
* tolerance - the tolerance level of the system oscillator.
*
* Return Values:
* CLASSB_TEST_PASS : return value = 0
* CLASSB_TEST_FAIL : return value = 1
******************************************************************************/
CLASSBRESULT CLASSB_ClockTest(uint32_t clockFrequency, uint32_t referenceFrequency, size_t msec, uint8_t tolerance)
{
uint32_t Clock_expectedCount;
uint32_t Clock_toleranceCount;
uint32_t systemFreq = clockFrequency/4;
//SETUP
CLASSB_ClockTestSetup();
CLASSB_timerCount = ((uint32_t)msec*referenceFrequency)/1000; //number of expected reference counts
if(CLASSB_timerCount == 0)
{
CLASSB_timerCount = 1;
}
Clock_expectedCount = 0;
Clock_expectedCount = (uint16_t)(((systemFreq*msec)/1000)/CYCLES); //number of expected system counts
Clock_toleranceCount = ((Clock_expectedCount*tolerance)/100);///CYCLES);
//TMR1 = 0;
set_timer1(0);
CLASSB_ClockTestTimer();
TMR1ON = 0;
if(CLASSB_Clockcount == 0)
{
CLASSB_ClockTestRestore();
return CLASSB_TEST_TIMEOUT;
}
if(CLASSB_Clockcount < (Clock_expectedCount - Clock_toleranceCount))
{
CLASSB_ClockTestRestore();
return CLASSB_TEST_FAIL;
}
if(CLASSB_Clockcount > (Clock_expectedCount + Clock_toleranceCount))
{
CLASSB_ClockTestRestore();
return CLASSB_TEST_FAIL;
}
CLASSB_ClockTestRestore();
return CLASSB_TEST_PASS;
}
void CLASSB_ClockTestTimer (void)
{
#asm
TimerTest:
BANKSEL (_CLASSB_timerCount)
MOVF BANKMASK(_CLASSB_timerCount)+1,W
BANKSEL TMR1H
NOP
SUBWF TMR1H,W
BTFSS STATUS, 0x2
GOTO IncCounter
NOP
NOP
NOP
NOP
// NOP
BANKSEL _CLASSB_timerCount
MOVF BANKMASK(_CLASSB_timerCount),W
BANKSEL TMR1L
SUBWF TMR1L, W
BTFSC STATUS, 0x0
GOTO TimerTestEnd
IncCounter:
BANKSEL (_CLASSB_Clockcount)
INCF BANKMASK(_CLASSB_Clockcount),F
BTFSC STATUS, 0x2
INCF BANKMASK(_CLASSB_Clockcount)+1,F
GOTO TimerTest
TimerTestEnd:
RETURN
#endasm
}
void CLASSB_ClockTestSetup(void)
{
//CLASSB_TRISC_temp = TRISC;
CLASSB_INTCON_temp = INTCON;
CLASSB_T1CON_temp = T1CON;
CLASSB_PIE1_temp = PIE1;
//TRISC0 = 1;
//TRISC1 = 1;
INTCON = 0;
T1CON = 0b10001000;
TMR1IF = 0;
TMR1IE = 1;
//TMR1 = 0xFE00;
set_timer1(0xFE00);
TMR1ON = 1;
while(!TMR1IF);
TMR1IE = 0;
TMR1IF = 0;
}
void CLASSB_ClockTestRestore(void)
{
//TRISC = CLASSB_TRISC_temp;
INTCON = CLASSB_INTCON_temp;
T1CON = CLASSB_T1CON_temp;
PIE1 = CLASSB_PIE1_temp;
}
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Gives Error 95 on BANKSEL (_CLASSB_timerCount)
I don't know how to solve this, does anyone know? |
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temtronic
Joined: 01 Jul 2010
Posts: 9229
Location: Greensville,Ontario
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| Posted: Fri Jan 24, 2020 10:03 am |
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I had a quick look......
I didn't see where this variable
_CLASSB_timerCount
is defined or created ??
There is this one.
uint16_t CLASSB_timerCount = 0;
but I seriously doubt you'd need 16 bits for 'bank selection' though without knowing what PIC is being used, hard to say....
Have to 'chuckle' about a computer testing itself for accurate speed... |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Fri Jan 24, 2020 12:08 pm |
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The CCS compiler automatically handles bank selection within an #asm
block. You don't have to do it. In the test program farther below, I create
a variable and assign its address as 0x300 in RAM. Notice in the .LST file
below, the compiler has inserted a MOVLB instruction to set the bank at 3:
| Quote: |
.................... #asm
.................... MOVWF MyVar
00036: MOVLB 3
00038: MOVWF MyVar
0003A: MOVLB 0
.................... #endasm
....................
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Test program:
| Code: | #include <18F46K22.h>
#fuses INTRC_IO, NOWDT, BROWNOUT, PUT, NOPBADEN
#use delay(clock=4M)
#use rs232(baud=9600, UART1, ERRORS)
#include <stdint.h>
uint8_t MyVar = 0;
#locate MyVar = 0x300
//======================================
void main()
{
#asm
MOVWF MyVar
#endasm
while(TRUE);
} |
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mvanvliet
Joined: 02 Jun 2009
Posts: 123
Location: The Netherlands
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| Posted: Wed Jan 29, 2020 2:56 am |
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@temtronic: As I've read the underscore is to switch from C to ASM with the same variable in the Microchip XC8 compiler. It is defined as uint16_t CLASSB_timerCount = 0;
@PCMprogrammer: So I need to remove the Banksel code and then the compiler should assign it to the correct bank or do I need to add the #locate code?
In this code I've removed the BANKSEL and changed the BANKMASK sentences, could this be working:
| Code: |
#asm
TimerTest:
//BANKSEL (_CLASSB_timerCount)
MOVF CLASSB_timerCount+1,W
//BANKSEL TMR1H
NOP
SUBWF TMR1H,W
BTFSS STATUS, 0x2
GOTO IncCounter
NOP
NOP
NOP
NOP
// NOP
//BANKSEL _CLASSB_timerCount
MOVF CLASSB_timerCount,W
//BANKSEL TMR1L
SUBWF TMR1L, W
BTFSC STATUS, 0x0
GOTO TimerTestEnd
IncCounter:
//BANKSEL (_CLASSB_Clockcount)
INCF CLASSB_Clockcount,F
BTFSC STATUS, 0x2
INCF CLASSB_Clockcount+1,F
GOTO TimerTest
TimerTestEnd:
RETURN
#endasm
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Wed Jan 29, 2020 3:29 am |
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| mvanvliet wrote: |
@PCMprogrammer: So I need to remove the Banksel code and then the
compiler should assign it to the correct bank or do I need to add the #locate code?
In this code I've removed the BANKSEL and changed the BANKMASK
sentences, could this be working:
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Yes, I compiled that code and looked at the .LST file, and it looks good.
The compiler inserts bank select instructions in the correct places.
The #locate code is put in there for my test. You don't normally use #locate.
Your code does not need it. |
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mvanvliet
Joined: 02 Jun 2009
Posts: 123
Location: The Netherlands
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| Posted: Wed Jan 29, 2020 4:37 am |
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Thanks for your reaction. Most of the errors I receive now are the ones for the function below.
The errors for EEADR and PMADR have I solved to add
#byte EEADR = getenv("DATA_EEPROM")
#byte PMADR = getenv("PROGRAM_MEMORY")
in the main .c program, is that correct?
But how to solve the PMCON bits? I can find CFGS and RD in the EECON1 register, but if the PIC doesn't have an EEPROM these bits are not used. So I don't know which they mean.
| Code: |
/******************************************************************************
* Description:
* This function reads the flash at the startAddress.
* Input:
* addr : the address of the flash memory to be tested
* Returns:
* EEDAT : The data in the flash address of addr
*
******************************************************************************/
uint16_t CLASSB_flashRead(uint16_t addr)
{
#ifdef _EECON1_RD_POSN //this will decide between EECON or PMCON for devices without EEPROM
EEADR = addr;
EECON1bits.CFGS = 0; // Do not select Configuration Space
EECON1bits.EEPGD = 1; // Do select Program Memory
EECON1bits.RD = 1; // Initiate read
#asm
NOP //
NOP //
#endasm
return EEDAT;
#else
PMADR = addr;
PMCON1bits.CFGS = 0; // Do not select Configuration Space
PMCON1bits.RD = 1; // Initiate read
#asm
NOP //
NOP //
#endasm
return PMDAT;
#endif
}
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Ttelmah
Joined: 11 Mar 2010
Posts: 19520
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| Posted: Wed Jan 29, 2020 5:12 am |
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| Quote: |
I can find CFGS and RD in the EECON1
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What processor?.
On some processors these bits are in the PMCON register instead of
EECON. The switch for this is controlled by 'EECON1_RD_POSN'.
If these are not in your EECON1 register, you need to #define
EECON1_RD_POSN, and use the PMCON register instead. |
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mvanvliet
Joined: 02 Jun 2009
Posts: 123
Location: The Netherlands
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| Posted: Wed Jan 29, 2020 5:13 am |
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The processor I would like to use for the Class B test is 16F15313 (which has CRC), which doesn't have an eeprom.
On the 16F1824 (which I've used in the past) these EEPROM register bits are findable.
Do you have a type in mind which do have the PMCON register? So I can check the datasheet. |
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temtronic
Joined: 01 Jul 2010
Posts: 9229
Location: Greensville,Ontario
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| Posted: Wed Jan 29, 2020 6:18 am |
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I was thinking about this code over the weekend...
comment.
You are aware that you'll have to compare the CCS version of the assembled code of this function to the original ?
void CLASSB_ClockTestTimer (void)
It appears this is the actual 'timer test', so every line of code has to be the same, otherwise the 'timing' will be incorrect.
Jay |
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