bug with PIC24FJ1024GA606 and 5.074

[gaugeguy]

I have submitted this to CCS already, but there is a strange bug that has shown up in version 5.074. Enabling interrupt on change tries to access some strange bits. Hopefully this may help someone else who may be having strange problems. I had a pin mysteriously getting pulled high when it should have been low.

V5.071
.................... enable_interrupts(INTR_CN_PIN|PIN_D5); // enable interrupt on CN14/RD5
1FD6C: BSET.B IOCPD.IOCPD5
1FD6E: BSET.B IOCND.IOCND5
1FD70: BSET.B PADCON.IOCON
1FD72: BSET.B IEC1.IOCIE
.................... enable_interrupts(INT_CNI); // enable interrupt IOC
1FD74: BSET.B IEC1.IOCIE


V5.072
.................... enable_interrupts(INTR_CN_PIN|PIN_D5); // enable interrupt on CN14/RD5
1FD6C: BSET.B IOCPD.IOCPD5
1FD6E: BSET.B IOCND.IOCND5
1FD70: BSET.B PADCON.IOCON
1FD72: BSET.B IEC1.IOCIE
.................... enable_interrupts(INT_CNI); // enable interrupt IOC
1FD74: BSET.B IEC1.IOCIE


V5.073
.................... enable_interrupts(INTR_CN_PIN|PIN_D5); // enable interrupt on CN14/RD5
1FD6C: BSET.B IOCPD.IOCPD5
1FD6E: BSET.B IOCND.IOCND5
1FD70: BSET.B PADCON.IOCON
1FD72: BSET.B IEC1.IOCIE
.................... enable_interrupts(INT_CNI); // enable interrupt IOC
1FD74: BSET.B IEC1.IOCIE

V5.074
.................... enable_interrupts(INTR_CN_PIN|PIN_D5); // enable interrupt on CN14/RD5
1FD52: BSET.B IOCFD.IOCFD5 // <-- write to read-only flag
1FD54: BSET.B IOCPUD.IOCPD5 // <-- enable pullup
1FD56: BSET.B PADCON.IOCON
1FD58: BSET.B IEC1.IOCIE
.................... enable_interrupts(INT_CNI); // enable interrupt IOC
1FD5A: BSET.B IEC1.IOCIE

[Ttelmah]

IOCFD.IOCFD5, is not read only.
It has to be changed to 0 in the handler routine. It is R/W.
However it is not legal to set it to 1 It should be being set to 0 to ensure the bit is not flagged as having caused an interrupt.

From the data sheet:
"Note 1: It is not possible to set the IOCFx register bits with software
writes (as this would require the addition of significant logic). To test
IOC interrupts, it is recommended to enable the IOC functionality on
one or more GPIO pins and then use the corresponding LATx register
bit(s) to trigger an IOC interrupt."

So correct to be writing to this register, but wrong to set it to 1.