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MikeW
Joined: 15 Sep 2003 Posts: 184 Location: Warrington UK
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OT:Pin selection on PIC16F1827 |
Posted: Sat Feb 20, 2010 2:56 am |
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I posted this on the microchip forum, but got no reply,
i know its not a CCS issue, but can any PIC guru's help me out here.
the 1827 has pin selection registers which allow for pin selection of the function.
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I am very confused about why Microchip has chosen such a strange pin selection setup.
Since the PIC16F1827 has 1x uart, 2xMSSP, so its has a potential for 1x UART, and a choice of either 2x I2C, 2xSPI, or 1xI2C and 1xSPI
why oh why have they chosen pin2 RB2 to allow it to be used as Tx,Rx,SDA2,SDO1,SDI2., similar for RB1,RB4, and RB5
I cant see a way of getting a configuration other than
1xUART and 1xI2C or 1xSPI, so why have 2 MSSP's ?
I would have thought that the pin selection would allow flexibility of
1x UART,1xI2C,1xSPI
it seem crazy to me
Mike |
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Ttelmah Guest
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Posted: Sat Feb 20, 2010 10:35 am |
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A Uart, is not seen as a particularly 'useful' peripheral for many standalone applications. With SPI being used to talk to memory, displays, etc., the UART is seen as something unlikely to be used. Hence much more useful to be able to get rid of this and have an I2C, or second SPI.
Best Wishes |
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MikeW
Joined: 15 Sep 2003 Posts: 184 Location: Warrington UK
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Posted: Sat Feb 20, 2010 11:59 am |
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Ttelmah,
I respect you as a long time poster.
But I don't understand your logic.
If the uart wasnt needed, and can't be used , why waste the silicon.
Once again, if the chip has 1xuart, and 2x MSSp, surely it should be able
to configure the pin selection register to use them.
This is rhetorical.
Mike |
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Ttelmah Guest
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Posted: Sat Feb 20, 2010 1:24 pm |
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The silicon is a few dozen gates.
The restricted feature is pins.
This is why more powerful chips allow you full 'pin selection', with you selecting which peripheral goes to which pins. However full selection involves a lot more silicon.
On this chip, you are being offered a choice of one MSSP, and a UART, _or_ 2*MSSP's.
Best Wishes |
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MikeW
Joined: 15 Sep 2003 Posts: 184 Location: Warrington UK
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Posted: Sun Feb 21, 2010 8:30 am |
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Ttelmah,
I totally agree that the pin count is the restriction, which is why a need for pin selection exists at all.
If "The silicon is a few dozen gates.", then why not allow 3 or 4 other pins to be in the pin selection agenda.
My point of posting was just to confirm that the 3 function blocks could not be used, only 2 out of 3.
Which you have confirmed. If I was a Microchip FAE, I would be a bit mad !!
So, one hardware block must be thrown away, which is a shame.
Mike |
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MikeW
Joined: 15 Sep 2003 Posts: 184 Location: Warrington UK
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extra info |
Posted: Wed Feb 24, 2010 1:12 am |
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got this reply from the microchip forum.
I need to check it out, but if true, its great news !!
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Mike,
Read section 12.1 "Alternate Pin Function" in the 16F1827 data sheet. All 3 serial comms can be used at once.
Using APFCON0,
-- Reassign RX/DT to RB1
-- Reassign SDO1 to RA6
This frees RB2 to be used as SDA2.
Maybe Microchip isn't so crazy after all.
Best Regards,
Ron |
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temtronic
Joined: 01 Jul 2010 Posts: 9174 Location: Greensville,Ontario
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Posted: Sat Dec 27, 2014 6:49 am |
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in carrying on 'silly pin usage' WHY the doubling up of VDD and VSS on PICs like the 18F46K22? Never had a problem using just one pair of power pins and who wouldn't like TWO more I/O pins to play with!
You'd also think uC would have had a better layout for the ICSP pins.
sigh too much stuff inside this blobs of epoxy these days !
Jay |
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