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KTrenholm
Joined: 19 Dec 2012
Posts: 43
Location: Connecticut, USA
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| Interrupts reading as invalid on compile? |
 Posted: Wed Dec 19, 2012 12:29 pm |
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Hello all,
I seem to be having a very strange issue with the CCS compiler.
I'm working with a PIC24FV32KA302 and v4.132 of the PCWHD IDE and compilers.
I'm having a very strange issue attempting to enable interrupts to trap failures in code. I'm looking to add isr functions for oscillator failures, address errors, stack errors, and math errors.
In theory this should be no issue. in the PIC24FV32KA302.h file all these interrupts are defined.
However when I add these interrupts and their corresponding | Code: | | enable_interrupts(INT_xxx); |
call, I get an error from the compiler:
Error 51 "A numeric expression must appear here :: not a valid interrupt"
This doesn't seem to make any sense as the numeric constants are defined and are listed in the valid interrupts. I haven't had any issue like this with any of the timer interrupts and I'm hoping someone can clue me in as to if I'm missing something.
My code for the ISRs is below. Right now they are just simple functions to hold the code in place:
| Code: | #int_OSCFAIL
void int_OSCFAIL(void)
{
while(1){restart_wdt();}
}
#int_ADDRERR
void ADDRERR_isr(void)
{
while(1){restart_wdt();}
}
#int_STACKERR
void STACKERR_isr(void)
{
while(1){restart_wdt();}
}
#int_MATHERR
void MATHERR_isr(void)
{
while(1){restart_wdt();}
} |
and here is the code for enabling the interrupts:
| Code: | void init_interrupts(void)
{
#use FAST_IO(A)
#use FAST_IO(B)
enable_interrupts(INT_TIMER1);
enable_interrupts(INT_TIMER2);
enable_interrupts(INT_TIMER4);
enable_interrupts(INT_SI2C);
enable_interrupts(INT_OSCFAIL);
enable_interrupts(INT_ADDRERR);
enable_interrupts(INT_STACKERR);
enable_interrupts(INT_MATHERR);
enable_interrupts(INTR_GLOBAL);
} |
Which is called after the processor pins, ADC, and timers have been configured and some various global variables have been initialized.
I would be grateful for any assistance anyone may be able to provide as I can't see anything I'm doing wrong. |
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temtronic
Joined: 01 Jul 2010
Posts: 9164
Location: Greensville,Ontario
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| Posted: Wed Dec 19, 2012 12:40 pm |
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quick comment...
1) might be a 'typo' from a line 'further up the line'.....
2) I'd go back to simpler code then just try one new ISR and see what happens...
keeping things 'small and simple', one step at a time approach usually will show what's wrong..
hth
jay |
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KTrenholm
Joined: 19 Dec 2012
Posts: 43
Location: Connecticut, USA
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| Posted: Wed Dec 19, 2012 12:54 pm |
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| temtronic wrote: | quick comment...
1) might be a 'typo' from a line 'further up the line'.....
2) I'd go back to simpler code then just try one new ISR and see what happens...
keeping things 'small and simple', one step at a time approach usually will show what's wrong..
hth
jay |
Thanks for the reply.
Just adding a single new interrupt seems to work fine.
I put in an RDA isr just now and it had no problems.
This code has been working fine with the exception of a hard to reproduce processor crash that I'm trying to debug via these interrupts.
The numeric constants are being brought in just fine.
They are defined in the device h file:
| Code: | #define INT_OSCFAIL 1
#define INT_ADDRERR 2
#define INT_STACKERR 3
#define INT_MATHERR 4 |
and they seem to be being brought into the interrupt_enable() function just fine.
I actually tried replacing the INT_xxx with just the constant 1 (for oscillator failure INT) and it just gives the same error.
It seems like it just isn't recognizing that these are valid interrupts for some reason? |
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FvM
Joined: 27 Aug 2008
Posts: 2337
Location: Germany
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| Posted: Wed Dec 19, 2012 1:25 pm |
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It might be helpful to consult the PIC24 family reference manual in this matter. The said soft traps are
non-maskable, there's no interrupt enable bit related to it. Thus interrupt_enable() can't work. |
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KTrenholm
Joined: 19 Dec 2012
Posts: 43
Location: Connecticut, USA
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| Posted: Wed Dec 19, 2012 1:34 pm |
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| FvM wrote: | It might be helpful to consult the PIC24 family reference manual in this matter. The said soft traps are
non-maskable, there's no interrupt enable bit related to it. Thus interrupt_enable() can't work. |
I took a look at the spec for this chip and I believe you are correct.
It seems there are no interrupt enable bits for these specific interrupts in the interrupt enable control registers.
So are these interrupts just enabled by default and only trigger an ISR if there's one defined at that vector? |
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FvM
Joined: 27 Aug 2008
Posts: 2337
Location: Germany
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| Posted: Thu Dec 20, 2012 7:55 am |
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| Quote: | | So are these interrupts just enabled by default and only trigger an ISR if there's one defined at that vector? |
It's all in the manual.
These events trigger a trap conflict reset if not handled by an ISR. That's the default behaviour e.g. with an
unhandled address error trap. |
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