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johnl
Joined: 30 Sep 2003 Posts: 120
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Timer1 Gate not working on PIC16F636 |
Posted: Wed Mar 28, 2012 3:09 pm |
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A biphase encoder's phase A output is wired to T1CKI (A5) and phase B is wired to T1G (A4). When the shaft rotates clockwise, phase A's rising edge coincides with a high on B, and in the other direction the rising edge coincides with a low on B.
However Timer1 is counting up in both rotation directions.
Timer1 is set up like this:
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#byte T1CON = 0x10
#byte CMCON1 = 0x1A
T1CON = 0b11000011;
CMCON1 = 0b00000010;
set_tris_a(0b00110001); // A0, A4, A5 inputs
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In a static test, grounding the gate inhibits counting as it should but the gate has no effect when connected to the encoder output. |
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Ttelmah
Joined: 11 Mar 2010 Posts: 19494
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Posted: Wed Mar 28, 2012 3:20 pm |
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It would do.
The gate, is just a logic input. Look at the diagram in the data sheet. If the edge has changed, then the gate releases, this will be seen as a count.
The counter only runs in one direction, so both movement directions will just give counts 'up' with your configuration....
Best Wishes |
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johnl
Joined: 30 Sep 2003 Posts: 120
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Posted: Thu Mar 29, 2012 8:53 am |
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Ttelmah wrote: | If the edge has changed, then the gate releases, this will be seen as a count.
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This is not clear to me on the logic diagram since the clock signal path is not directly gated with the gate signal. Also the data sheet states that Timer1 is incremented on the "rising edge" of T1CK1.
The diagram suggests that if the EN input to the counter is not high, the counter will not count. Furthermore the data sheet suggests that the counter is edge triggered, not level triggered. If it were truly edge triggered, holding the clock high while the EN goes high should not increment the counter. Apparently, this is not the case.
Thanks. |
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Ttelmah
Joined: 11 Mar 2010 Posts: 19494
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Posted: Thu Mar 29, 2012 9:41 am |
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No. You are not reading the data sheet properly. If you look at Fig 6.1, the gate signal is taken, and fed through a programmable inverter (top right corner of the diagram), then logically combined with the enable signal, and feeds into an _and_ gate with the incoming signal. Now, 'yes' the timer counts rising edges, but if the incoming signal is _high_ and the gate signal into the and gate goes 'high', the circuit will generate a rising edge on it's output, which will then be counted. Clock _pulses_ that have occurred, while the gate is off, will be missed, but if the pulse is still active when the gate re-enables, it _will_ be counted. The logic is quite explicit.
Best Wishes |
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johnl
Joined: 30 Sep 2003 Posts: 120
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Posted: Thu Mar 29, 2012 9:51 am |
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I must be looking at a different Figure 6-1 diagram. I follow your description until
" into an _and_ gate with the incoming signal."
On my diagram that _and_ gate has TMR1ON for the other input, not the "incoming signal" which I assume you mean "clock signal."
For reference, the diagram is on this page: DS41232D-page 65 |
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Ttelmah
Joined: 11 Mar 2010 Posts: 19494
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Posted: Thu Mar 29, 2012 10:08 am |
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Mines an original release 'A' paper data sheet. Nicely shows the and gate immediately to the right of the actual timer counter.
Sounds as if Microchip decided they were telling us too much!....
Best Wishes |
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