CCS C Software and Maintenance Offers
FAQFAQ   FAQForum Help   FAQOfficial CCS Support   SearchSearch  RegisterRegister 

ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

CCS does not monitor this forum on a regular basis.

Please do not post bug reports on this forum. Send them to support@ccsinfo.com

handling two interrupts.... how????

 
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion
View previous topic :: View next topic  
Author Message
gokulrred



Joined: 22 Nov 2011
Posts: 32
Location: puducherry

View user's profile Send private message Send e-mail

handling two interrupts.... how????
PostPosted: Wed Jan 11, 2012 6:09 am     Reply with quote

i want to use SSP interrupt for spi....

and while SSP ISR completes my program will make hardware to generate interrupt.

that interrupt i am using in CCP1...

is it possible?
asmallri



Joined: 12 Aug 2004
Posts: 1634
Location: Perth, Australia

View user's profile Send private message Send e-mail Visit poster's website

Re: handling two interrupts.... how????
PostPosted: Wed Jan 11, 2012 7:48 am     Reply with quote

gokulrred wrote:
i want to use SSP interrupt for spi....

and while SSP ISR completes my program will make hardware to generate interrupt.

that interrupt i am using in CCP1...

is it possible?


Some PICs support multiple interrupt vectors. The PIC18F supports high and low, the PIC24 and dsPIC support multiple. The PIC16F supports only a single interrupt vector.

PICs with multiple vectors support multiple priority levels. The PIC18F (the most basic PIC supporting multiple vectors) has a high priority vector and a low priority vector. The PIC24 and dsPICs have multiple levels of priority.

For PICs with multiple interrupt vectors, a higher priority interrupt will interrupt a lower priority interrupt handler.

CAUTION: The CCS compiler has a different concept of interrupt priorities which predated PICS with unique vectors per source. This priority is used to determine the interrupt handler processes interrupts of the SAME hardware priority HOWEVER by default when an interrupt occurs interrupts of the same or lower hardware priority are disabled. Unless you really know what you are doing, you should not enable interrupts of the same priority inside the interrupt handler.

Back to your specific case, There is NO reason that processing SSP interrupts should take more than a few clock cycles. If it does then you have a logic error in your coding. For example, in an interrupt handler if you are writing out a data value you should never wait inside the handler for the byte to have been sent.
_________________
Regards, Andrew

http://www.brushelectronics.com/software
Home of Ethernet, SD card and Encrypted Serial Bootloaders for PICs!!
gokulrred



Joined: 22 Nov 2011
Posts: 32
Location: puducherry

View user's profile Send private message Send e-mail

PostPosted: Wed Jan 11, 2012 10:12 pm     Reply with quote

Thank you for your valuable comments...

I am using PIC 18F4431.
Code:

#int_SSP
SSP_isr()
{
val1 = spi_read();
if(val1==0x80)
  {
   output_bit(PIN_C6,1);
   output_bit(PIN_C7,0);
   delay_ms(10);
   output_bit(PIN_C6,0);
  }
}

The above code I've written in SSP ISR,
so when slave PIC gets SPI data it'll get interrupted.
Upon which it makes C6 =1 and C7=0.

In those ports I connect motor.
When the motor rotates its encoder generate pulse.

That pulse I want to take in CCP1.

1. My doubt is how to implement this ?
2. As soon as motor gets power for 10ms, it gets rotated and encoder generates pulse. Will it give an interrupt before the last line "output_bit(PIN_C6,0);" gets over ?

How to handle the interrupts ?
I want SSP to have high priority and CCP1 low priority.
Ttelmah



Joined: 11 Mar 2010
Posts: 19369

View user's profile Send private message

PostPosted: Thu Jan 12, 2012 2:31 am     Reply with quote

Which is why you should never delay in interrupts....
The simple rule is that an interrupt should do what is necessary to handle the hardware event it signals, and nothing else.
You should just read the spi in the SPI interrupt. Then if the value is the one you need to set the bits, set these, and either set a flag, then clear the bit in your main a few mSec latter, or start a hardware timer, to trigger 10mSec latter, and when this interrupts, then use it to clear the output bit.
Delays in an interrupt of more than a very few uSec, kill the whole point of using interrupts.

Best Wishes
gokulrred



Joined: 22 Nov 2011
Posts: 32
Location: puducherry

View user's profile Send private message Send e-mail

PostPosted: Fri Jan 13, 2012 6:41 pm     Reply with quote

@Ttelmah:

ya sir...
using delay will be not a good idea...

but i want to make D6 =0 and D7=1 when i get 0x80 data throu SPI.
and D6=1 and D7=0 when i get 0x81 data throu SPI in the slave side.

in both cases i want to make those terminals in that state and make them zero in 10 ms.

is there any other way to implement this?
Ttelmah



Joined: 11 Mar 2010
Posts: 19369

View user's profile Send private message

PostPosted: Sat Jan 14, 2012 2:58 am     Reply with quote

Yes I've already told you how to do it.....
Just use another timer ISR to clear the bits 10msec later.

Best Wishes
Display posts from previous:   
Post new topic   Reply to topic    CCS Forum Index -> General CCS C Discussion All times are GMT - 6 Hours
Page 1 of 1

 
Jump to:  
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum


Powered by phpBB © 2001, 2005 phpBB Group