geolover
Joined: 08 Feb 2011
Posts: 18
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| Prolem with SPI frame Sync mode on PIC24FJ128GA010 #inc |
 Posted: Wed Mar 16, 2011 5:52 pm |
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Hello everyone!
I'm trying to initialise a spi interface as frame sync master and spi master(i.e, outputting both frame sync pulse and free-running serial clock). However, my problem is that although I'm getting data on SDO pin and clockage on SCLK pin, there is no frame sync-pulse appear whatsoever, I'm using ccs compiler v4.117:
Here is my code:
| Code: |
#include <24FJ128GA010.h>
#FUSES NOWDT //No Watch Dog Timer
#FUSES NOJTAG //JTAG disabled
#FUSES NOPROTECT //Code not protected from reading
#FUSES NOWRT //Program memory not write protected
#FUSES NODEBUG //No Debug mode for ICD
#FUSES NOCOE //Device will reset into operational mode
#FUSES NOIESO //Internal External Switch Over mode disabled
#FUSES PR //Primary Oscillator
#FUSES CKSNOFSM //Clock Switching is enabled, fail Safe clock monitor is disabled
#FUSES NOOSCIO //OSC2 is clock output
#FUSES XT
#bit frmen2 = 0x0264.15
#bit spifsd2= 0x0264.14
#bit spifpol2=0x0264.13
#bit spife2 = 0x0264.1
//#bit msten2 = 0x0262.2
#bit cke2 = 0x0262.8
#bit ckp2 = 0x0262.6
#use delay(clock=8000000)
#use rs232(UART1,baud=9600,parity=N,bits=8)
void main()
{
int8 i;
frmen2 = 1; //frame enable
// msten2 =1;
spifsd2 =0; //frame sync output
spifpol2=0;//frame sync polarity is active high
spife2 =1;//frame sync pulse coincide with spi data
// cke2 =0;
// ckp2 =1;
setup_spi(SPI_MASTER | SPI_CLK_DIV_4);
//setup_spi2(SPI_SS_DISABLED);
setup_spi2(SPI_MASTER | SPI_H_TO_L | SPI_XMIT_L_TO_H | SPI_CLK_DIV_4);//set spi 2 to master mode, cke=0, ckp=1, clock frequency is 8MHz divided by 4
while(1)
{
for (i=0;i<256;i++)
{
spi_write2(0xFFFF);
delay_us(10);
spi_write2(0xFF);
delay_us(10);
}
}
// setup_wdt(WDT_ON);
// setup_timer1(TMR_DISABLED|TMR_DIV_BY_1);
// TODO: USER CODE!!
}
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