| View previous topic :: View next topic |
| Author |
Message |
a21
Joined: 01 May 2010
Posts: 10
|
| PIC18F24J50 and internal RTC |
 Posted: Tue Jan 18, 2011 5:21 am |
 |
|
Hi,
I have problem with the internal RTC. Here are part of my code:
main.h
| Code: |
#include <18F24J50.h>
#FUSES NOWDT //No Watch Dog Timer
#FUSES WDT128 //Watch Dog Timer uses 1:128 Postscale
#FUSES STVREN //Stack full/underflow will cause reset
#FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES NODEBUG //No Debug mode for ICD
#FUSES NOCPUDIV
#FUSES NOPROTECT //Code not protected from reading
#FUSES HSPLL //High speed Osc (> 4mhz for PCM/PCH) (>10mhz for PCD)
#FUSES PLL1
#FUSES T1DIG
#FUSES NOLPT1OSC //Timer1 configured for low-power operation
#FUSES NOFCMEN //Fail-safe clock monitor enabled
#FUSES NOIESO //Internal External Switch Over mode enabled
//#FUSES DSWDTOSC_INT
#FUSES RTCOSC_T1
#FUSES NODSBOR
#FUSES NODSWDT
#FUSES DSWDT2
#FUSES NOIOL1WAY //Allows multiple reconfigurations of peripheral pins
#FUSES MSSPMSK7
#FUSES NOWPFP
#FUSES WPBEG
#FUSES NOWPCFG
#FUSES WPDIS
#use delay(clock=48000000)
|
main.c:
| Code: |
#byte EECON2 = 0xFA7
#byte RTCCFG = 0xF3F
#byte INTCON = 0xFF2
#DEFINE GIE 7
#DEFINE RTCWREN 5
void RTCC_unlock(void)
{
#asm ASIS
movlb 0x0F ;//RTCCFG is banked
bcf INTCON, GIE ;//Disable interrupts
movlw 0x55
movwf EECON2
movlw 0xAA
movwf EECON2
bsf RTCCFG,RTCWREN
#endasm
}
setup_oscillator(OSC_PLL_ON|OSC_TIMER1);
RTCC_unlock();
setup_timer_1(T1_EXTERNAL|T1_ENABLE_T1OSC|T1_DIV_BY_1);
setup_timer_3(T3_DISABLED|T3_DIV_BY_1);
setup_timer_4(T4_DISABLED,0,1);
setup_comparator(NC_NC_NC_NC);
setup_timer_0(RTCC_INTERNAL | RTCC_EXT_L_TO_H | RTCC_DIV_1 | RTCC_8_BIT); //enables internal RTCC
while(1)
{
....
}
|
I can set the date and time, but it doesn't change. Each time I read it is the same. I am using external crystal on T1 32.768KHz and 6.8pF capacitors. |
|
 |
Ttelmah
Joined: 11 Mar 2010
Posts: 19504
|
|
| Posted: Tue Jan 18, 2011 8:37 am |
|
|
There seem to be several conflicting clock settings. Not sure what the result will really be.
You have the master oscillator set as 'HSPLL', which implies an external crystal > 4MHz, but then PLL1 selected, which says feed the PLL from clock/1, and implies the crystal should be 4Mhz.
Then you have IESO disabled, but then use a setup_oscillator line, saying to start running the CPU from the t1 oscillator, but with the PLL still enabled (which does nothing if T1 OSC is selected). This is presumably being ignored because of the fuse setting. However the data sheet says 'selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the reference clock of Section 2.6 “Reference Clock Output”) and PLL".
Then you setup T1, which looks correct.
Then you configure the RTCC module to use both the internal oscillator and the external clock input. You can only have one or the other here....
Er.....
Best Wishes |
|
|
a21
Joined: 01 May 2010
Posts: 10
|
|
| Posted: Tue Jan 18, 2011 8:55 am |
|
|
| Here is the thing. I am using 4MHZ with PLL primary oscillator because of the USB (and it is working). I have another crystal on T1OSI/T1OSO which is 32.768KHz. I want to use the RTCC with this crystal. |
|
|
Ttelmah
Joined: 11 Mar 2010
Posts: 19504
|
|
| Posted: Tue Jan 18, 2011 9:35 am |
|
|
Yes, I understood that. Your basic settings are _wrong_. You are just getting away with it, because most are illegal.
'setup_oscillator', controls the CPU oscillator. You already have this setup with the fuses, you don't want to be saying 'use the T1 oscillator for the CPU', which is what your line says.
Then on the Timer0, you are enabling both internal, and external operation. Look at the circuit in the data sheet. Is this allowed?.
You don't want T1DIG (you have already said not to allow the secondary oscillator).
You may well find if you set things correctly, things start working. It may not, but then at least it is not a random result of odd settings, causing the problem.
Best Wishes |
|
|
a21
Joined: 01 May 2010
Posts: 10
|
|
| Posted: Tue Jan 18, 2011 9:49 am |
|
|
I made some changes:
main.h:
| Code: |
#include <18F24J50.h>
#FUSES NOWDT //No Watch Dog Timer
#FUSES WDT128 //Watch Dog Timer uses 1:128 Postscale
#FUSES STVREN //Stack full/underflow will cause reset
#FUSES NOXINST //Extended set extension and Indexed Addressing mode disabled (Legacy mode)
#FUSES NODEBUG //No Debug mode for ICD
#FUSES NOCPUDIV
#FUSES NOPROTECT //Code not protected from reading
#FUSES HSPLL //High speed Osc (> 4mhz for PCM/PCH) (>10mhz for PCD)
#FUSES PLL1
#FUSES NOT1DIG
#FUSES NOLPT1OSC //Timer1 configured for low-power operation
#FUSES NOFCMEN //Fail-safe clock monitor enabled
#FUSES NOIESO //Internal External Switch Over mode enabled
//#FUSES DSWDTOSC_INT
#FUSES RTCOSC_T1
#FUSES NODSBOR
#FUSES NODSWDT
#FUSES DSWDT2
#FUSES NOIOL1WAY //Allows multiple reconfigurations of peripheral pins
#FUSES MSSPMSK7
#FUSES NOWPFP
#FUSES WPBEG
#FUSES NOWPCFG
#FUSES WPDIS
#use delay(clock=48000000)
|
main.c:
| Code: |
#include <main.h>
#include <pic18_usb.h>
#include <descriptor.h>
#include <usb.c>
#byte EECON2 = 0xFA7
#byte RTCCFG = 0xF3F
#byte INTCON = 0xFF2
#DEFINE GIE 7
#DEFINE RTCWREN 5
void RTCC_unlock(void)
{
#asm ASIS
movlb 0x0F ;//RTCCFG is banked
bcf INTCON, GIE ;//Disable interrupts
movlw 0x55
movwf EECON2
movlw 0xAA
movwf EECON2
bsf RTCCFG,RTCWREN
#endasm
}
void main()
{
setup_oscillator(OSC_PLL_ON);
setup_timer_1(T1_ENABLE_T1OSC|T1_DIV_BY_1);
setup_timer_3(T3_DISABLED|T3_DIV_BY_1);
setup_timer_4(T4_DISABLED,0,1);
RTCC_unlock();
setup_rtc(RTC_ENABLE,0);
while(1)
{ .... }
} |
Still the same problem. |
|
|
a21
Joined: 01 May 2010
Posts: 10
|
|
| Posted: Tue Jan 18, 2011 12:07 pm |
|
|
| Solved |
|
|
|
FAQ 
Search
Register
Profile 
Log in to check your private messages 
Log in
