| View previous topic :: View next topic |
| Author |
Message |
petu65
Joined: 05 Jan 2011
Posts: 8
|
| 18F4523 PEIE and ADIF registers |
 Posted: Wed Jan 05, 2011 7:50 am |
 |
|
I have used following code for 18F452 to read adc in sleep mode:
| Code: |
#bit PEIE=0xFF2.6
#bit ADIF=0xF9E.6
#use delay(clock=4000000,RESTART_WDT)
long int true_adc (void)
{
long int adc=0;
enable_interrupts(INT_AD);
PEIE=1;
ADIF=0;
read_adc(ADC_START_ONLY);
sleep();
disable_interrupts(INT_AD);
adc=read_adc(ADC_READ_ONLY);
return adc;
}
setup_adc_ports(ALL_ANALOG|VSS_VDD);
setup_adc(ADC_CLOCK_INTERNAL);
|
Now I am moving to 18F4523 and can't find correct register values for PEIE and ADIF. Is there better way to do this for accurate adc values? |
|
 |
Ttelmah
Joined: 11 Mar 2010
Posts: 19513
|
|
| Posted: Wed Jan 05, 2011 10:29 am |
|
|
You don't need either register. You are already enabling the interrupt with your 'enable interrupt' line. You just need 'clear_interrupts(INT_AD)' to clear the flag if it is already triggered (which is what your 'ADIF=0' does).
Hopefully you are not using any other interrupts?. If you are, you need to disable these, or they could trigger the wake up, before the ADC has finished....
The register values are in the data sheet.
Best Wishes |
|
|
petu65
Joined: 05 Jan 2011
Posts: 8
|
|
| Posted: Fri Jan 07, 2011 8:08 am |
|
|
| Could you give me example how to do adc readings in sleep mode with 18F4523? I just don't understand what are correct adc clock values with 4Mhz oscillator if I use just read_adc()? Last two bits in adc reading are always unstable. I have 1,5V battery in AN0 for testing and VDD is clean. |
|
|
Ttelmah
Joined: 11 Mar 2010
Posts: 19513
|
|
| Posted: Fri Jan 07, 2011 9:57 am |
|
|
Seriously, stable readings are down to good design. VDD, is never a 'good' Vref. Remember you are looking at just 5mV for a step. "Clean"... The reading will be affected by fluctuations above the frequency resolvable by most DVM's, but too small to be visible on most scopes....
Your 'ground', is also as important as the Vdd layout.
I routinely see completely stable ADC readings, without bothering with 'sleep', but am using a ground plane, and a separate Vref.
Look at the data sheet. Table 19-1. _Lowest_ divider, who's maximum clock rate is above yours. /4 for 4MHz.
When asleep, the only clock is the internal clock. The master CPU clock stops when you sleep. Problem with this when 'awake', is that since it is not synchronous to the CPU clock, you can get a 'beat' effect as the number of cycles of the CPU clock vary in the sample...
Best Wishes |
|
|
|
FAQ 
Search
Register
Profile 
Log in to check your private messages 
Log in
