Parallel Master Port (PMP) communication with PIC18F67J50

[cassis]

This is my assebly programm for PMP module.
The PMDIN1L Reg is in the subroutine, but there isn't bus activity for write on the board.
All PMP port pins (PMA 8 - 13, PMD 0- 7, PMCS1, PMCS2, PMWR, etc.) are logical zero.
where is mistake in program?



LIST P=18F67J50
#include <P18f67J50.INC>

CONFIG DEBUG = OFF ;Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
CONFIG XINST = OFF ;Instruction set extension and Indexed Addressing mode disabled
CONFIG STVREN = OFF ;Reset on stack overflow/underflow disabled
CONFIG PLLDIV = 1 ;No prescale (4 MHz oscillator input drives PLL directly)
CONFIG WDTEN = OFF ;WDT disabled (control is placed on SWDTEN bit)
CONFIG CP0 = OFF ;Program memory is not code-protected
CONFIG CPUDIV = OSC1 ;[No CPU System clock divide]
CONFIG IESO = OFF ;Two-Speed Start-up disabled
CONFIG FCMEN = OFF ;Fail-Safe Clock Monitor disabled
CONFIG FOSC = HSPLL ;HS oscillator, PLL enabled, HSPLL used by USB
CONFIG WDTPS = 1 ;1:1
CONFIG MSSPMSK = MSK5 ;5 Bit address masking
CONFIG CCP2MX = DEFAULT ;ECCP2/P2A is multiplexed with RC1

#define 0 access
#define 1 banked

org 50
goto start

start:
movlb d'15'

movlw B'10001011'
movwf PMCONH,banked

movlw B'01111111'
movwf PMCONL,banked

movlw B'00000010'
movwf PMMODEH,banked

movlw b'00000000'
movwf PMMODEL,banked

movlw b'11111111'
movwf PMEH,banked

movlw b'00000011'
movwf PMEL,banked

movlw b'10010111'
movwf PMADDRH,access

movlw b'11111111'
movwf PMADDRL,access



PMPwrite:
btfsc PMMODEH,BUSY,banked
goto PMPwrite
movlw b'11011011'
movwf PMDIN1L,banked ;write data to PMP bus
goto PMPwrite

end

[PCM programmer]

You're on the wrong forum. This is the CCS forum for their C compilers.
You need the Microchip forum:
http://www.microchip.com/forums/m467125.aspx