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i2c slave is holding scl low

 
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johnbravado



Joined: 07 Apr 2010
Posts: 11

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i2c slave is holding scl low
PostPosted: Thu Jun 24, 2010 8:14 am     Reply with quote

I am having an issue where my slave PIC16F886 is holding the SCL low, i am assuming to clk stretch. However, since CCS is doing all the i2c work, is there a way to make the pic release the scl line. what is confusing is i am working with another company on a project and we need to talk to each other via i2c.

I will try and explain to set the scene.
I have a slave module i will call module A
I have a master module, module B
they have a master module, module C
they have a slave module, module D

I am only having problems in a read command. so read goes
start->address | read->ack->command->ack->restart->address | write->ack->data->ack->scl is held low at this point

If i connect Module A to module B i do not have a problem with this command, it works fine.
If I connect module C to module D, i do not have this problem.
It is only when i connect module A to module C

If i force the SCL pin high by jumpering over the 4.7k pullup, the system continues doing its routines. until it gets to this call again then it freezes.

Any ideas on what may be causing this problem? or is their a way to force the release of the clk of the i2c hardware?
rnielsen



Joined: 23 Sep 2003
Posts: 852
Location: Utah

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PostPosted: Thu Jun 24, 2010 9:08 am     Reply with quote

The CKP bit in the SSPCON register controls if the slave will hold the SCL line low to stretch it out. You might try setting this bit (CKP) after the slave sends it's data to ensure the SCL line is released. I've manipulated this bit before to ensure the master waits for the slave to finish it's job.

Also, make sure your master sends a NACK on it's last i2c_read(0) command to tell the slave that it's finished talking.

Ronald
johnbravado



Joined: 07 Apr 2010
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PostPosted: Thu Jun 24, 2010 9:17 am     Reply with quote

Thanks. If the master does not send an ack after receiving the data i send it. would that cause the pic to hold the SCL line low?
Ttelmah



Joined: 11 Mar 2010
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PostPosted: Thu Jun 24, 2010 9:25 am     Reply with quote

You realise that the master should _NACK_ the last byte on a read from the slave i2c_read(0). This is _vital_.

Best Wishes
johnbravado



Joined: 07 Apr 2010
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PostPosted: Thu Jun 24, 2010 9:57 am     Reply with quote

yes i do realize, and i see a blurp where the master tries to send an ack, but then i hold the scl low so the master cant send a stop.

I tried adding the following in hopes to try and force the slave clk hold off. is this the proper way to change a register?

Code:

/***MAIN.c***/
#byte SSPCON = 0x14 //the SSPCON special registor is located 14h so you dont have to look up the datasheet.

void main(void){
     set_bit(SSPCON, 4); //does this set the CKP bit high thus disengages the clock hold function. the CKP bit is bit 4
}
rnielsen



Joined: 23 Sep 2003
Posts: 852
Location: Utah

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PostPosted: Thu Jun 24, 2010 11:24 am     Reply with quote

I, normally, just declare both like this:
Code:
#byte SSPCON = 0x14
#bit CKP = SSPCON.4

Each bit can be declared for this register and each one can be manipulated by:
Code:
CKP = 1;

This just makes for less needed typing (I can be a bit lazy at times) and also helps to remember what each bit is used for.

Ronald
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