SPI VS Parallel

[logical]

Hi Guys/Gals,

Just to try and help people avoid the confusion about which to choose, IMHO the Parallel may be a better option, sure you have more data lines to contend with BUT I have found the throughput to be far faster and easier to debug and less subject to noise.

A comparison I found on another forum is stated below further clarifies this, the part I am currently experimenting with SEPS525a supports 8/16bit SPI and also 8/9/16bit Parallel, I will be trying a 24h series processor over parallel, firstly will try with the PSP port, then will give it a go with port B (16io's) and post data via 16bit thereby totally exceeding the speed of the SPI by a factor of approx 13.2x.

Anyway, have a look for yourself on the comparisons below, if anyone deems this to be incorrect then please add to this post.

Hope this helps.

Chris

The following was based on an 8bit screen.

Parallel theoretical Max clock:
1 / 300nanoseconds = 3,333,333.33Hz or 3.33MHz

SPI theoretical Max clock:
1 / 250nanoseconds = 4,000,000.00Hz or 4.00MHz

Parallel theoretical Max datarate:
1 / ( 300 nanoseconds) * 8 bits = 25.4313151Mb/s (3.17891439MB/s)

SPI theoretical Max datarate:
1 / ( 250 nanoseconds) * 1 bits = 3.81469727Mb/s (0.476837158MB/s)

so its nearly 6.66x as fast.

Also by using Parallel, you can also read the Screen RAM which not supported through SPI on Screens I have been using.

[ckielstra]

I don't know where your values are coming from but I like the precisions of your calculations with up to 9 digits after the dot they must be correct.

Assuming the fastest PIC18 at 64MHz:
Gives for both SPI and instructions a maximum frequency of: 64MHz/4 = 16MHz
Loading new data and storing to the output register is a loop of about 4 instruction cycles (might be 5, I haven't checked).

SPI: The instruction loop is not the limiting factor but clocking out the data is. Resulting in 16MBit/sec / 8 bits = 2Mbyte/sec
Parallel 8 bits, in the loop of instructions cycles = 16MHz / 4 instructions = 4Mbyte/sec

So yes, parallel is faster (2x, not 6.66x).

What the best solution is depends on your project. Many PIC processors have a low number of I/O pins, then it often is more important to save on the pin count than to have the highest speed possible.

[languer]

Not sure on the intent of the original message; but it sounded like you already had the answer, and wanted a question to go with it

It would seem that for almost any application, parallel would be faster than serial. But it really all depends on what you're interfacing with. Let me provide a few examples (other than available I/O) in which parallel becomes just too expensive (not only $).

1) Take a 32-bit addressing path and 32-bit data path. If doing this on a board, you may run into real-state issues with all those lines running across the board. Also have to consider keeping the lines matched for impedance and length; and separate to avoid crosstalk. However, you will see that most high speed ADCs/DACs/Memories are addressed through a parallel interface.

2) Take the same 32-bit system and now off-boarded. Now you have multiple times the weight of a simple serial bus. And you also have to protect all those lines from external interference (or from causing external interference.

Like ckielstra mentioned, it depends on your application and your trade-offs. Personally, unless I have to do otherwise I prefer the simpler interfaces.

[logical]

Was not intended that way, personally I have had a fair pain in the backside with the SPI on the high res oled screens and was just sharing the info I found with others, the calculations were not mine as stated in the first post, the original thread they came from was

http://forum.sparkfun.com/viewtopic.php?p=19260&sid=d57a214545612ad81d84abf1492cbaae