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kdoney34711
Joined: 05 Oct 2009
Posts: 6
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| PCD: #use delay() |
 Posted: Mon Oct 05, 2009 8:24 am |
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On all of the usb to serial examples, when you use the 24FJ256GB110 an error arises from trying to use the #use rs232 without having done a #use delay. What is the delay for this chip?
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KDONEY |
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FvM
Joined: 27 Aug 2008
Posts: 2337
Location: Germany
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| Posted: Mon Oct 05, 2009 8:45 am |
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| In USB operation, it's usually a fraction of the PLL VCO frequency of 96 MHz, selectable are 32, 16, 8 or 4 MHz. |
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kdoney34711
Joined: 05 Oct 2009
Posts: 6
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| Posted: Mon Oct 05, 2009 8:51 am |
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On all of the other chips they are using the pll speed. For instance, on the pic explorer 16 they use
| Code: | | #use delay(clock=32M) //8MHz clock is 4x because of PLL |
and the others are the same. If the pll for the 24F is 96 MHz shouldn't I use 96M?
The whole section is
| Code: |
#if __USB_PIC_EXPLORER16__
#use delay(clock=32M) //8MHz clock is 4x because of PLL
#fuses PLL2 //Divide 8MHz by 2 to get the 4MHz required for USB |
if this helps answer the question. They change a fuse after setting delay.
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KDONEY |
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FvM
Joined: 27 Aug 2008
Posts: 2337
Location: Germany
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| Posted: Mon Oct 05, 2009 1:20 pm |
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| Quote: | | For instance, on the pic explorer 16 they use |
The question, what you use respectively intend to use. I can't know.
With PIC24FJxxGB, the VCO must run at 96 MHz (if used at all), the PLL fuses have to be set to achieve this frequency with the respective crystal. Then, with PR_PLL in effect, the default cpu clock is 32 MHz. It can be divided down by setting CPDIV1:CPDIV0 bits in CLKDIV register. But I guess, you're satisfied with default 32 MHz. |
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Guest
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| Posted: Tue Oct 06, 2009 1:50 pm |
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I usually verify by scoping a pin and put
| Code: |
while (1)
{
output_high(pin_a0);
delay ms(1);
output_low(pin_a0);
delay ms(1);
}
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This proves you have the right settings. |
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bkamen
Joined: 07 Jan 2004
Posts: 1615
Location: Central Illinois, USA
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| Posted: Tue Oct 06, 2009 8:27 pm |
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Look VERY carefully at page pdf page 118 (or 116 of the datasheet).
It shows very clearly how the PLL branches with a MAX output frequency of 32MHz for the CPU core.
So #USE DELAY (clock=32M) is what you want for max speed.. (less if you use the CPDIV bits to divide down)
-Ben
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Dazed and confused? I don't think so. Just "plain lost" will do. :D |
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