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Guest
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| 18F4550 oscillator configuration |
 Posted: Fri Jun 12, 2009 8:15 am |
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I'm new to USB equipped micros and am using a pic18f4550 with a bootloader and 20mhz crystal. I'm also using the uart for serial comms to an lcd screen @115,200 baud. I have been able to get it to work utilizing empirical problem solving methods but I don't fully understand why. I've got a few questions below, if anyone has any knowledge they would like to share or know of some good links i would be much obliged. Here are the pertinent fuse settings:
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#FUSES HSPLL //External Clock with PLL enabled and Fosc/4 on RA6
#FUSES PLL5 //Divide By 5(20MHz oscillator input)
#FUSES CPUDIV1 //No System Clock PostScaler
#FUSES USBDIV //USB clock source comes from PLL divide by 2
#FUSES VREGEN //USB voltage regulator enabled
#FUSES ICPRT //ICPRT enabled
#use delay(clock=48000000)
#use rs232(baud=115200,parity=N,xmit=PIN_C6,rcv=PIN_C7,bits=8,ERRORS,) |
1. From the datasheet it shows CPUDIV options as 2,3,4,6 in HSPLL mode. Why does CCS not allow a CPUDIV6 setting?? and why does CCS allow a CPUDIV1 setting when this is not shown as an option in the datasheet? Ironically, CPUDIV1, ie no postscaler is the setting which allows serial comms. to function.
2. What function does the CPUDIV setting serve, ie if the mcu is clocked at 48MHz and CPUDIV is 4, does that mean the mcu is now executing instructions at 12MHz?
3. If the 4x PLL is enabled, ie clock mode set to HSPLL, and i'm using a 20mhz crystal, should the #use delay setting not be 40mhz??...using 40mhz allows the code to execute, ie led's flash etc, but serial only communicates when this setting is at 48mhz...why?? |
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Guest
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| Posted: Fri Jun 12, 2009 8:24 am |
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| correction to the third one, typo....20mhz w/PLL should #use delay not be set at 80mhz??...how is #use delay related to the actual clock speed, or is it not related at all? |
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Ttelmah
Guest
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| Posted: Fri Jun 12, 2009 9:42 am |
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Really, the CPUDIV bit, is down to the way Microchip did things. They have four divider 'values', which give /1, /2, /3, and /4, when the external oscillator is used, and /2, /3, /4, and /6, when the internal USB clock is used. The CCS fuse 'numbers', refer to the external oscillator dividers, and they can hardly offer a duplicate set for the internal oscillator, since two of the ratios are duplicated. So it just comes 'up to you', to remember that the CCS numbers refer to the internal dividers, and remember that you have to translate when using the internal divider. It'd really have been 'better' for CCS, not to have used the division 'number', and just code their fuses as CPUDIV00, CPUDIV01, CPUDIV10, and CPUDIV11, but the 'division number' standard was used on older chips that didn't have the two 'paths', so they stuck with the old numbering...
When you select 'HSPLL', it means that the CPU clock, is alwys going to come from the USB clock source, which is always 96MHz, if USB2 is used/working. You could instead divide from the external clock, by just selecting 'HS'. The PLL still runs, but now only feeds the USB section, and your available CPU clocks would become 20MHz (CPUDIV1), 10MHz (CPUDIV2), 6.66MHz (CPUDIV3), and 5MHz (CPUDIV4).
There is no '*4' PLL on these chips. The PLL, is fixed at *24, and is designed to only really work from a 4Mhz source, with a progammable divider in front of it.
Best Wishes |
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