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steve1986 Guest
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Last minute Question-PIC clocks to DAC |
Posted: Mon Apr 27, 2009 2:19 am |
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Hi everyone! I have been struggling with the timing issue of my PIC for a few weeks and still have no success. If anyone could please help me out I would greatly appreciate it. The demo is tomorrow and I am pretty disappointed...
I have read and tried to use timer0, timer1, and timer2 to set up some clocks that my DAC needs(not in the following codes). The problem is, I need to load DATA to the DAC as well. Every time I tried to load the DATA on the line all the clocks slow down. I need decently fast clocks (for speech), and aiming for the max clock to be at least 1MHz. I am using a 40MHz crystal. Loading the DATA also causes my clocks to have weird periods...(some pulses are longer than the others).
The three clocks I need have the following relationship:
System clock = 128*fs, Back clock = 32*fs, and Leftright clock = fs, where I am using fs = 8kHz. I am using PCM 1770 from TI and PIC18F.
Here's my codes:
Code: | // DAC TEST PROGRAM
#include <16F877A.h>
int16 sample[2][10] = {
0x8E00,0xC200,0x8300,0x7D00,0x7E00,0x6B00,0x7400,0x8F00,0xA700,0xB500,
0x9B00,0x6E00,0x4800,0x2D00,0x4100,0x2D00,0x2A00,0x2200,0x1A00,0x2200
};
#define BCLK PIN_C7
#define DATALINE PIN_C6
#define LRCLK PIN_C5
#define SYSCLK PIN_C4
#use delay(clock = 10000000)
void output_DAC(long DAC_Data)
{
int c;
int d;
c = 0;
// Left bits
output_high(LRCLK);
for(d = 15; d != -1; d--)
{
output_bit(DATALINE, bit_test(DAC_Data, d));
for (c = 0; c < 2; c++)
{
output_high(SYSCLK);
output_low(SYSCLK);
}
output_high(BCLK);
d++;
for (c = 0; c < 2; c++)
{
output_high(SYSCLK);
output_low(SYSCLK);
}
output_low(BCLK);
}
d = 0;
output_low(LRCLK);
for(d = 15; d != -1; d--)
{
output_bit(DATALINE, bit_test(DAC_Data, d));
for (c = 0; c < 2; c++)
{
output_high(SYSCLK);
output_low(SYSCLK);
}
output_high(BCLK);
d++;
for (c = 0; c < 2; c++)
{
output_high(SYSCLK);
output_low(SYSCLK);
}
output_low(BCLK);
}
}
void DAC_Sample()
{
int c, r;
// Initial clock state
output_low(BCLK);
output_low(SYSCLK);
output_low(LRCLK);
for (c = 0; c < 250; c++)
{
for (r = 0; r < 10; r++)
output_DAC(sample[c][r]);
}
}
void main()
{
int i = 0;
int ts, tb;
int bitindex;
int colindex;
int rowindex;
long databyte;
setup_timer_0(RTCC_INTERNAL |RTCC_DIV_256 );
set_timer0(0);
setup_timer_1(T1_INTERNAL | T1_DIV_BY_1);
set_timer1(0);
databyte = sample[colindex][rowindex];
// timer interval for timer bits
tb = 0;
ts = 0;
//tempbit = temp.1;
while(1)
{
}
} |
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Ttelmah Guest
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Posted: Mon Apr 27, 2009 4:09 am |
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First, of course it will.
At 40MHz, the processor only performs 10MIPS. Now, even a single bit test, and branch, will probably involve at least 5 instruction times, and if the compiler is being efficient, will take different times according to the result. There is no way you are going to get to 1Mhz (only 5 instructions for each half cycle), working in software, and no way the loop ses are going to remain symmetrical, without using slower coding. You are also using standard I/O, so every output instruction itself, will take three clock cycles....
Second, why do you care?. The whole point about synchrnous communications, is that the master controls the clock rate, sending the clock along with the data, so it doesn't matter if there is a variation during transmission....
Third, use hardware. This is what it is there for. The SPI hardware, is designed to do exactly what you seem to be trying to do, in hardware, at fixed clock rates, so you don't have this problem.
It is a bit like a bicyclist asking 'why can't I pedal at 100mph'. Basically in normal situations, you just physically can't generate the energy needed to overcome wind resistance, and the drag from bearings etc., to go at this speed. Then, when by using fabulous streamlining, and super efficient tyres etc.,he does manage to reach this speed, he seems surpirised when the speed drops on hills....
Best Wishes |
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