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kashif12
Joined: 24 Feb 2011 Posts: 8
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understanding PWM 18F2520 |
Posted: Sun Feb 27, 2011 5:49 am |
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Greetings world,
I need help to understand PWM generator in 18F2520.
Sorry if my questions are very basic.
I want to generate PWM signal on ccp1 (duty cycle 52.12 to 59.98) at 300khz depending on the input voltage (0-5V) converted by ADC in range (0-1023).
Now as I am using internal oscillator which can have max clock=8MHz right?
I am using following code:
Compiler V.4
Code: |
#include <18F2520.h>
#device adc=10
#fuses XT,NOWDT,NOPROTECT,BROWNOUT,PUT,NOLVP
#use delay(clock=4000000)
//what will be the effect of clock on ADC and PWM?
//================================
void main()
{
int8 value;
setup_ccp1(CCP_PWM);
setup_timer_2(T2_DIV_BY_1, 255, 1);
/*
>>mode?: i dont understand what is T2_DIV_BY_1
>> period?: will ensure duty cycle can vary from 0-1023 i.e. (0 percent to 100 percent) right?
how can i restrict it to 50.22 to 59.98?
postscale?: is a number 1-16 that determines how many timer overflows before an interrupt: (1 means once, 2 means twice, and so on).
what is this overflow?
*/
setup_port_a(AN0);
setup_adc(ADC_CLOCK_DIV_1);
//does mode value means here convert faster if div_1,slower if div_4 even slower if div_16?
///i mean is it increasing sensitivity?
set_adc_channel(0);
delay_us(20);
while(1)
{
value = read_adc();
set_pwm1_duty(value);
//if value is 512 or 1023 does this mean duty cycle will be 50% or 100%?
//how can i make duty cycle in 50.29?
//
}
} |
_________________ Mr Operating Systems |
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Ttelmah
Joined: 11 Mar 2010 Posts: 19367
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Posted: Mon Feb 28, 2011 9:45 am |
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First, what you post, is not using the internal oscillator. XT, is the external crystal oscillator.
Second. No, you are not limited to 8MHz, with the internal oscillator. Look at section 2.6.4 of the data sheet. You can go up to 32MHz with the PLL.
Now, you cannot 'restrict the range to 50.22 to 59.98. This is down to _you_ You will need to write your code, to restrict the range of values it feeds into the PWM setting.
However, you also have a potential problem about speeds. You want a 300Khz output frequency. This is just 106 cycles of the master clock (assuming you are running at 32Mhz). The PWM, _counts_ in master processor clock pulses, or a subdivided version of these (This is the T2_DIV_BY_1 - you can have the master clock, or the clock/4, or the clock/16). To get close to 300KHz, from a 32MHz master clock, needs:
setup_timer_2(T2_DIV_BY_1, 26, 1);
and allowable values for the width, will be just 0 to 107.
Now, another problem. You have 'value' selected as an int8, but are using it to hold a 10bit value from the ADC....
Then the ADC clock. Read the data sheet. There is a _minimum_ clock time that must be met for the ADC to work. Table 19-1, gives the allowable selections. For a 32Mhz master clock, you need clock/32.
With the '26' selected above, the output frequency will be:
32000000 / (4*27) = 296296Hz.
The pulse width counts in single cycles of the incoming clock (as opposed to the processor cycles - /4 for the main timing). So you want an on time of 1.674uSec to 1.999uSec. So, 53.5 to 64 cycles of the clock for the 'on time' Since you can't do half cycles, you will have to choose between 53 to 64, or 54 to 64 cycles. These are the counts that will need to be fed into the pwm_duty function. Just ten ot eleven possible values.....
The postscale overflow, does nothing, unless you are using the timer interrupt for something. At the speed you want to run, there is not time for this anyway.....
So you would have to take the value from the adc _in an int16_ divide it by say 93, and add 53, to give the nearest 'miss' to the required range. Resolution will be poor though.
Best Wishes |
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kashif12
Joined: 24 Feb 2011 Posts: 8
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thanks |
Posted: Mon Feb 28, 2011 10:23 am |
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Bundle of thanks Ttelmah.
I will go through data sheet and modify my code. _________________ Mr Operating Systems |
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