rtos semaphore

[FutheFuFu]

Hi all,

I'm using a PIC 18f6722 with ccs compiler4.065. I have a problem the the rtos and the BankSelectRegister(BSR) not being updated:

I have a task declared as follows:

#task(rate=1000ms,max=10ms)
void task_first()
{
char i;
rtos_wait(sem);
i = 1;
rtos_signal(sem);
}

The following is the listing data:
.................... void Task_First ( )
.................... {
.................... char i;
....................
.................... rtos_wait(sem);
*
0001C: MOVLW 2A // saving the lower part of the location of the rtos_wait(sem) command
0001E: MOVLB 5 // The BSR is updated
00020: MOVWF xE8
00022: MOVLW 00 // saving the higher part of the location of the rtos_wait(sem) command
00024: MOVWF xE9
00026: MOVLW 00 // saving the upper part of the location of the rtos_wait(sem) command
00028: MOVWF xEA
0002A: MOVF xE2,W //This is the location on the rtos_wait() command
0002C: SUBLW 00
0002E: BNC 0036
00030: BSF xE3.0
00032: GOTO 01EC
00036: DECF xE2,F
00038: BCF xE3.0
.................... i=1;
0003A: MOVLW 01
0003C: MOVWF xFD
.................... rtos_signal(sem);
0003E: INCF xE2,F
.................... }
00040: MOVLW 1C
00042: MOVWF xE8
00044: MOVLW 00
00046: MOVWF xE9
00048: MOVLW 00
0004A: MOVWF xEA
0004C: GOTO 01EA
00050: MOVLB 0
00052: RETLW 00

The location of the "sem" variable is in bank5.

The fisrt time the task is executed, the location of the "rtos_wait(sem)" instruction is saved in memory and then the "rtos_wait(sem)" instruction is executed. While saving the instruction location care is taken to keep the BankSelectRegister (BSR) pointing to the correct memory bank. If sem = 0, the rtos will yield and another task is given time to execute. When this task is executed again the saved location of the "rtos_wait(sem)" instruction is loaded into the programcounter. The problem that I have is that at this point the BSR is not updated again and if it was changed in another task the wrong ram loacation is tested by the instruction.

Is there anyone with any sugestions?