SPI bus, 3.3V Master, 5V Slave

bwhiten · Joined: 26 Nov 2003 Posts: 151 Location: Grayson, GA

The bus would be between two PICs as in the subject line. Will I need a level translator between the two for clock, DI and DO?
Master = 18F67J50, slave = 16F887.

Matro · Guest

Here is the classical level shifter for I²C bus.
w w w . nxp . com / news / backgrounders / bg_esc9727 / images / bg_esc9727_1. jpg
Remove the spaces I insert to be able to post this link. ;-)

It perfectly applies here.

Matro.

PCM programmer · Joined: 06 Sep 2003 Posts: 21708

That method is intended for i2c. There are several IC's that
incorporate that method. Example:
http://focus.ti.com/docs/prod/folders/print/pca9306.html

For SPI translators, read this thread:
http://www.ccsinfo.com/forum/viewtopic.php?t=23154

bwhiten · Joined: 26 Nov 2003 Posts: 151 Location: Grayson, GA

From these replies I take the answer is yes. I have a very nice bidirectional level translator from TI I already use, TXB0104 that can handle some extreme speeds at 3.3 to 5 and is very reasonably priced for 4 I/O.
Does any one see any issue with this component that I haven't noticed?
Also the TXS0104 series for open-drain drivers like I2C.