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adc drift with 18f2523

 
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waranet



Joined: 05 Jan 2006
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Location: France

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adc drift with 18f2523
PostPosted: Wed Aug 08, 2007 7:49 am     Reply with quote

Hello, I'm using a pic 18lf2523 with external crystal at 20 MHz. Sometimes I see a small drift in the adc measure, maybe 4 or 5 digits, one measure only, then the measure stays very stable for a while.

I have implemented a loop with 10 consecutive measures and I do the average but the problem still remains.

I would like to know if I need a delay between the read_adc. Actually I read the adc with any delay in the loop. I hope somebody has worked on this device, my CCS is V4.

thanks
jp
Ttelmah
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PostPosted: Wed Aug 08, 2007 8:42 am     Reply with quote

At 'heart', all the PIC ADC's are very similar in behaviour. They involve an internal capacitor being charged to the input voltage _and then disconnected from this voltage while the conversion is made_. As such, it is vital to have the source connected to the capacitor, long enough for the voltage on this to get within 0.5 of a bit value, before a conversion is made. Since the capacitor is disconnected during the conversion, it is necessary to have a delay between samples.
Now there are a lot of bits that affect the answer to your question.
What is your clock speed?. (this will affect how quick the 'loop' is likely to be).
What have you set the Tad to?.
What is the source impedance of the circuit feeding the ADC input?.
What is your Vref?. (you will _not_ get reliable 12bit operation from Vdd).
Have you got Tacqt set?.
As an example, if you are running off 32MHz, then if you setup the ADC, with:

setup_adc(ADC_CLOCK_DIV_32|ADC_TAD_MUL_4);

The converter will automatically acquire for the Tad time, times 4 (Tacqt). Since Tad here is setup for 1uSec (32MHz/32), this gives the required pause (minimum 2TAD, between readings, or 2.96uSec from an input change).
Your source impedance should be below 2.5KR, and I'd suggest a Vref, something like the Intersil X60008-41, if you want full accuracy. Obviously careful track layout round the chip is also vital.
If you are using interrupts, disable them for the duration of the sample (otherwise the changes in system noise if an ISR is called during a sample, will ruin repeatability...).
For the best accuracy, consider using a sleep between starting the ADC, and reading it (look at the read_adc entry in the manual, for how this is done). With the automatic acquire time programmed, this gives the best performance of all.

Best Wishes
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