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Guess
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| RTCC doubt |
 Posted: Tue Mar 13, 2007 1:58 am |
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Hi, I've check the ex_stwt.c for the rtcc isr, there's some part i dun understand.
Below is the code :
| Code: | #include <16F84>
#fuses XT,NOWDT,NOPROTECT
#use delay(clock=20000000)
#use rs232(baud=9600, xmit=PIN_A3, rcv=PIN_A2)
#define INTS_PER_SECOND 76 // (20000000/(4*256*256))
byte seconds; // A running seconds counter
byte int_count; // Number of interrupts left before a second has elapsed
#int_rtcc // This function is called every time
clock_isr() { // the RTCC (timer0) overflows (255->0).
// For this program this is apx 76 times
if(--int_count==0) { // per second.
++seconds;
int_count=INTS_PER_SECOND;
}
}
main() {
byte start;
int_count=INTS_PER_SECOND;
set_rtcc(0);
setup_counters( RTCC_INTERNAL, RTCC_DIV_256);
enable_interrupts(RTCC_ZERO);
enable_interrupts(GLOBAL);
do {
printf("Press any key to begin.\n\r");
getc();
start=seconds;
printf("Press any key to stop.\n\r");
getc();
printf("%u seconds.\n\r",seconds-start);
} while (TRUE);
} |
How to get 1 second interrupt ?
From the formula (20000000/(4*256*256)) = 76, from where it got the info? the 20000000 is xtal freq, the /4 is the internal clock divider, the 256 is RTCC_DIV_256, wat about the other 256?
Why it needs to be set to 76 in order to get 1sec intr from a 20Mhz clock? |
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Ttelmah
Guest
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| Posted: Tue Mar 13, 2007 4:06 am |
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The counter itself, counts from 0 to 255. It then interrupts, and wraps back to zero. The counter 'source', is the processor clock over 4. So, each 'count', takes:
(20000000)/(4*256) = 1/19512.25th second
So the complete interrupt cycle (256 counts), takes:
19512.25/256 = 1/76.29th second
The '76' number, is rounding this down, and will give a slight error (about 0.38%).
If you search the forum, routines have been publishd several times in the past, using a simple integer arithmetic add and compare technique, to give exact timings for this type of setup, by adding one extra count occassionally. However unless total precision is needed, the error is very small.
Best Wishes |
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rnielsen
Joined: 23 Sep 2003
Posts: 852
Location: Utah
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| Posted: Tue Mar 13, 2007 8:18 am |
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If you have down loaded the spec. sheet, look at the section that describes Timer0. Figure 5-1 shows a simplified block diagram of the internal hardware. Fosc/4 is the crystal frequency divided by 4. This is a hardware design that cannot change. Then you have a pre-scaler that can be adjusted from 1:1 to 1:256. This is, basically, a counter that, if it is set to 256, will output one pulse for every 256 pulses that enter it. This, in turn, goes to another counting register that cannot be bypassed. It is an eight bit counter so it will output one pulse for every 256 pulses that enter it. Therefore, you have the formula of Fosc/4/256/256.
Like Ttelmah said, if you are running at 20MHZ you will have a slight error. If you need exactness then using a crystal of 19.6608MHZ will make your Timer0 ISR interrupt 75 times a second. You can have a counter increment each time the ISR is entered and then set a flag to give you a signal each second.
Hope this helps.
Ronald |
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