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theteaman
Joined: 04 Aug 2006
Posts: 98
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| spi having corrupt data? |
 Posted: Tue Jan 02, 2007 7:31 am |
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Hello
I am trying to connect two PICs together. The master PIC sends data to the slave PIC.
Something really odd happens - the data retrieved is sometimes wrong. For example, I have a loop where I send/receive a '1' from the master PIC to the slave PIC, and sometimes I get a '3'!
Would anyone have any idea why this could be the case? I tried slowing down the SPI (SPI_CLK_DIV_64) to no avail.
Thanks
Master (sender) code
| Code: |
#define SPI_MODE_0_0 0x4000
#define SPI_MODE_0_1 0x0000
#define SPI_MODE_1_0 0x0010
#define SPI_MODE_1_1 0x4010
void main(void)
{
setup_spi(SPI_MASTER | SPI_MODE_0_0 | SPI_CLK_DIV_4);
set_tris_c(0b00000011);
while(1)
{
while(!input(SIG)); //wait for signal to send data (slave PIC starts spi_read())
delay_us(10);
spi_write(2);
etc.....
etc.....
etc.....
etc.....
}
}
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ps. also could someone tell me, which has less speed overhead in an 18F, UART or SPI? |
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ckielstra
Joined: 18 Mar 2004
Posts: 3680
Location: The Netherlands
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| Posted: Tue Jan 02, 2007 9:29 am |
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Which PIC are you using?
What parameters do you have for the setup_spi() in your slave? |
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Ttelmah
Guest
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| Posted: Tue Jan 02, 2007 9:41 am |
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There are a lot of 'bits' to this.
First, the key advantage of SPI, is that a byte is transferred _both_ ways at the same time. Also, since it is synchronised by the master clock, there are no timing problems with different crystals/stability of the oscillators on the two chips.
What do you mean by 'speed overhead'?. Both these transfers, assuming the hardware is used, use no overhead in the transmitting/sending devices, except to read/write the byte. The maximum transfer rate, is from SPI, which can clock right up to the processor clock/4.
Now on your 'code', you don't show enought to give any idea of what is wrong. You read a signal line, waiting for it to go high. Which pin is this? I is presumably being set high by the slave to say it is ready for a transmission?. If so, why?. The point is that with SPI, the master controls the transfer. You can send the byte at any time from the master, and _then_ retrieve it from the buffer in the slave, whenever you want. Because the transfer is buffered at both ends, there is no need for the slave to signal at all. This is wasting a line. If you want the slave to 'initiate' the transfer, then make _it_ the master. Have the sending device 'preload' the data to send, and load the next byte, once the slave has retrieved it.
The 'odds' are that a data problem, is a result of using the wrong edge fro transmission/sampling at one end.
Best Wishes |
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theteaman
Joined: 04 Aug 2006
Posts: 98
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| Posted: Tue Jan 02, 2007 3:12 pm |
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| ckielstra wrote: | Which PIC are you using?
What parameters do you have for the setup_spi() in your slave? |
I am using two 18F2525s. The parameter for the slave is:
| Code: |
setup_spi(SPI_SLAVE | SPI_MODE_0_0 | SPI_CLK_DIV_4); |
| Quote: |
Which pin is this? I is presumably being set high by the slave to say it is ready for a transmission?. If so, why?. The point is that with SPI, the master controls the transfer. You can send the byte at any time from the master, and _then_ retrieve it from the buffer in the slave, whenever you want. Because the transfer is buffered at both ends, there is no need for the slave to signal at all. This is wasting a line. |
I changed the master and slave around but the problem is still the same :/. But I figured out the solution, as you said - by changing to SPI_MODE_0_1, it now works... Can you explain what this actually means because I assumed both modes should work if master/slave are configured correctly??
Thanks |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Tue Jan 02, 2007 3:42 pm |
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There's an errata on the B4 silicon for the SPI slave mode.
(There are tons of other erratas in the earlier silicon revisions).
http://ww1.microchip.com/downloads/en/DeviceDoc/80282a.pdf
It says there must be a minimum of 3 instruction cycles between the
falling edge of Slave Select and the first SCK clock. Try adding
the line shown in bold below to your Master PIC's code.
| Quote: |
output_low(SS_PIN);
delay_cycles(5);
spi_write(0x55);
output_high(SS_PIN); |
Also, post your crystal frequency and your compiler version. |
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theteaman
Joined: 04 Aug 2006
Posts: 98
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| Posted: Wed Jan 03, 2007 1:36 am |
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| PCM programmer wrote: | There's an errata on the B4 silicon for the SPI slave mode.
(There are tons of other erratas in the earlier silicon revisions).
http://ww1.microchip.com/downloads/en/DeviceDoc/80282a.pdf
It says there must be a minimum of 3 instruction cycles between the
falling edge of Slave Select and the first SCK clock. Try adding
the line shown in bold below to your Master PIC's code.
| Quote: |
output_low(SS_PIN);
delay_cycles(5);
spi_write(0x55);
output_high(SS_PIN); |
Also, post your crystal frequency and your compiler version. |
Hi PCMProgrammer
Is slave select optional? Because I am using that pin.. I can change it though.. |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Wed Jan 03, 2007 1:55 am |
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It's enabled by default when you setup an SPI slave. You have to
explicitly disable it, if you don't want it. Do that by OR'ing in the
constant shown in bold below. This is for your Slave PIC only.
| Quote: | | setup_spi(SPI_SLAVE | SPI_MODE_0_0 | SPI_CLK_DIV_4 | SPI_SS_DISABLED); |
Also, post your crystal frequency. Or, if you're using the PLL post
your clock frequency. |
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theteaman
Joined: 04 Aug 2006
Posts: 98
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| Posted: Wed Jan 03, 2007 2:14 am |
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| PCM programmer wrote: | It's enabled by default when you setup an SPI slave. You have to
explicitly disable it, if you don't want it. Do that by OR'ing in the
constant shown in bold below. This is for your Slave PIC only.
| Quote: | | setup_spi(SPI_SLAVE | SPI_MODE_0_0 | SPI_CLK_DIV_4 | SPI_SS_DISABLED); |
Also, post your crystal frequency. Or, if you're using the PLL post
your clock frequency. |
Thanks for that, I disabled /SS. My crystal is 20MHz. |
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PCM programmer
Joined: 06 Sep 2003
Posts: 21708
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| Posted: Wed Jan 03, 2007 12:33 pm |
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It may not work reliably with an SCLK frequency of 5 MHz.
The PIC's data sheet wants a setup and hold time of 100 ns (each)
for data to SCLK edge. That's for the Master or the Slave, when
receiving data.
I suggest setting the SCLK speed to the next lower setting:
SPI_CLK_DIV_16
Do that in both the Master and the Slave PICs. |
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