Again: problems with two i2c on the same PIC

Santi · Guest

I have the same problem reported by Ants: "Dual I2C implementation on a PIC using CCS", but no solution was posted there. How was it solved?

Its a PIC16LC717. As soon as the hardware I2C (slave) is addressed and interrupts during a communication on the software I2C bus, the SDA line of the hardware i2c is held down for a very long time, crashing the communication.

The configuration directives for both I2C streams are:

#use i2c(stream=A,slave,sda=PIN_B4,scl=PIN_B2,force_hw,slow,address=0x68)
#use i2c(stream=B,master,sda=PIN_B1,scl=PIN_B0,force_sw,slow )

CCS PCM C Compiler, Version 4.011

Does anybody have any suggestion, please?

Thanks!

Ttelmah · Guest

The I2C SDA line, _will_ be held low, till the data transaction can proceed. Basically, if the master is asking to read data from the slave, the line will hold low, till the moment that the slave writes data to the output register. You need to check your code in the ISR, and verify that data _is_ being written. If the ISR handling is wrong, and data is not written, the behaviour will be as described.

Best Wishes

rnielsen · Joined: 23 Sep 2003 Posts: 852 Location: Utah

The Slave will hold the SDA line low if it is not finished doing something. This tells the Master to wait and give it time to do whatever the Slave is needing to do. The Master will be in the 'wait' mode and not send anymore clock pulses out until the Slave releases the SDA line. Check the code in your Slave to make sure it's not holding the line low. The CKP bit (look in the spec sheet for the correct register bit) is the one that will control this. When I write code for a Slave I clear this bit at the beginning of my ISR to ensure that the Master will wait until the PIC is ready to continue. Then, when the program is ready, I will set the CKP bit and allow the Master to continue on it's way.

If the SDA line is held low by the Slave the Master will wait forever and appear to be hung.

Ronald

Mark · Joined: 07 Sep 2003 Posts: 2838 Location: Atlanta, GA

The slave should be holding the SCL line low, not the SDA. This is known as clock stretching and allows the slave time to process the request. If a slave device held the SDA line low, the master would continue to transmit until the master writes a high level. At this point, the master loses arbitration and must relinquish the bus in case another master is trying to communicate.

PCM programmer · Joined: 06 Sep 2003 Posts: 21708

Santiago Moronho Arenas · Joined: 18 Oct 2006 Posts: 4 Location: Galicia

Thank you very much PCM programmer! You never believe integrated cicuits can have bugs, but they do. Or is it a compiler bug for not taking in account this issue when both i2c buses are on the same port?

Never mind.

We've moved the software i2c bus to the other port and assured all tris bits sharing port with the hardware i2c are fixed IN or OUT. It works OK now!

Thanks again for your help!
And also to the other guys/[spam] answering.
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Santi - Itelsis