I2C Multi Master mode

Wayne_ · Joined: 10 Oct 2007 Posts: 681

CCS PCH C Compiler, Version 4.011, 26184

I am curently trying to make I2C Multi Master mode work between a pic 18F6722 and an arm processor. Both state they do multi master and I have had some success.

Arm works as master and slave (Multimaster)
Pic works as master only (Multimaster mode)

When I enable the SSP and BUSCOL interrupts on the PIC for slave (multimaster) opperation I get a problem.

1st I issue a start, get an interrupt SSP1STAT = 0x88 but then the write hangs.
I then restart the pic (not the arm) and the start creates a bus collision.
SSP1STAT = 0x80 prior to the i2c_start and after the BUSCOL interrupt.

It works ok except for pic not being able to work in slave mode using interrupts with the interrupts dissabled.

I havn't posted any code because all I want to know is:-

What I would like to know is what actually does the MULTIMASTER setting in the #use i2c statement do ?

I assumed that if the pic does a start command then it enables the clock output. If it does a write statement without a start then it puts the data in the spi buffer to be clocked out by the other master!

Wayne_ · Joined: 10 Oct 2007 Posts: 681

It's OK I worked out what the differences were myself. Didn't need to create a new project for it, just change the setting and looked at the .lst file without the #nolist setting.

Wayne_ · Joined: 10 Oct 2007 Posts: 681

I have just foud a problem with I2C MultiMaster mode with the PIC. From the datasheet :-

"SSPxADD register holds the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator reload value."

Does this mean that when just before I switch to master mode (send a start) I have to load this with the Baud rate reload value and after sending a stop load it with the slave address ?