ADC sampling rate for filter design

[Guest]

Hello UG:

I am using an 18F452 device in 4x PLL mode with an external 10 MHz clock source. I use ADC in a loop to grab many samples of the same channel continuously with no other interruption until all my data is collected. Instead of doing an average (or median or moving average) to reduce noise, I was thinking of using an IIR filter. When using software to design the filter, the user must specify the desired frequency response of the filter, as well as the sampling rate. I know my desired frequency response, but I am not sure of the correct sampling rate to use. Can I set a pin high, grab ADC data, then set the pin low and use a scope to measure the time between the pin high states to infer the sampling rate? Is this the best way, or can it be computed in advance knowing the clock rate? Any advice or pitfalls to be had from others having tried this before? I am aware of IIR stability issues, but the relatively short length of the IIR is very attractive. Right now, I must average like heck to reduce random sensor noise and the latency is a bother. I will try any tricks....

Thanks very much,
Vlad

[rwyoung]

I believe the PIC18F has a maximum sampling rate around 30ksps. This assumes you go into a tight loop and start a new sample as soon as the last is complete. Doesn't leave you much time for doing anything else.

And this assumes you are driving the ADC input with a low impedance output such as an op-amp. The data sheet shows you how to calculate the acquisition time for the specific PIC, clock speed and drive impedance.

There are some PIC18Fs that have a sampling time of around 10us which would be nearly 100ksps if you did nothing else except service the ADC.

Make sure your analog circuit doesn't have any more bandwidth than 1/2 your sampling frequency so you don't have serious problems with aliased components in your data.
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Rob Young
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