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CCP_COMPARE_RESET_TIMER

 
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Ken Johnson



Joined: 23 Mar 2006
Posts: 197
Location: Lewisburg, WV

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CCP_COMPARE_RESET_TIMER
PostPosted: Thu Aug 23, 2007 9:02 am     Reply with quote
Please educate me on the use of this feature:

In this code example, the 1st interrupt occurs at 1 msec, as expected, but subsequent interrupts occur at 13 msec, the timer overflow period.

My understanding from the data sheets is that timer3 should reset, the compare register remain unchanged, and that all these interrupts would be at 1 msec interval (until I change the compare register).

Obviously, I've missed something - can some good soul straighten me out?

Thanks,
Ken

code snippet:
Code:

#INT_CCP4
void    CompareISR (void)
{
    ToggleTP1 ();
}

void    main (void)
{
    setup_timer_3 (T3_DIV_BY_1 | T3_INTERNAL);
    setup_ccp4 (CCP_COMPARE_RESET_TIMER | CCP_USE_TIMER3);
    TP1 (1);
    set_timer3 (0);                 //  Reset Timer3;
    CCP_4 = (TimerCounts (1e-3));   //  Interrupt at 1 msec;
    clear_interrupt (INT_CCP4);
    enable_interrupts (INT_CCP4);
    enable_interrupts (GLOBAL);

    for ( ;; ) {
        delay_ms (250);
    }
}

18F8722, tried both CCS V3.2439 and 4.052 - same results;
Kenny



Joined: 07 Sep 2003
Posts: 173
Location: Australia

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PostPosted: Thu Aug 23, 2007 5:11 pm     Reply with quote
The setup code and the asm produced by version 3.249 looks OK to me.

The code is not complete, so I used CCS output_toggle() and output_high() on an 18F252 with CCP2, just setting CCP_2 to a value (it doesn't have CCP4). It worked OK.

Your problem is probably with the code not shown.

Cheers
Another Ken
Ken Johnson



Joined: 23 Mar 2006
Posts: 197
Location: Lewisburg, WV

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PostPosted: Thu Aug 23, 2007 5:28 pm     Reply with quote
Knew I should include all of it:

Code:
//  Filename:   PCH TestCCP.c   Copyright © 2007 K & N Co.
//  Created:    Aug 23, 2007    by Ken Johnson
//  Purpose:

#define CRYSTAL     20000000

#include "18F8722.h"
#device ICD=TRUE
#fuses  DEBUG,NOWDT

#fuses  HS
#use delay(clock=CRYSTAL,RESTART_WDT)
#use RS232 (DEBUGGER,DISABLE_INTS)

#define CLOCKFREQ   (0.25 * CRYSTAL)    //  Internal clock is 1/4 crystal frequency;
#define TimerCounts(seconds)    ((int16) (CLOCKFREQ * (seconds) + 0.5))
#define TP1(on)         output_bit (PIN_B0, on)
#define ToggleTP1()     output_toggle (PIN_B0)

#INT_CCP4
void    CompareISR (void)
{
    ToggleTP1 ();
}

void    main (void)
{
    setup_timer_3 (T3_DIV_BY_1 | T3_INTERNAL);
    setup_ccp4 (CCP_COMPARE_RESET_TIMER | CCP_USE_TIMER3);
    TP1 (1);
    set_timer3 (0);                 //  Reset Timer3;
    CCP_4 = (TimerCounts (1e-3));   //  Interrupt at 1 msec;
    clear_interrupt (INT_CCP4);
    enable_interrupts (INT_CCP4);
    enable_interrupts (GLOBAL);

    for ( ;; ) {
        delay_ms (250);
    }
}
Kenny



Joined: 07 Sep 2003
Posts: 173
Location: Australia

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PostPosted: Fri Aug 24, 2007 3:01 am     Reply with quote
The debugger could be the problem. I don't have one to do any testing.
Try NODEBUG.

Other than that the code worked with CCP2 on the 18F252 with the following fuses:
#fuses HS,NOWDT,NOPROTECT,PUT,BROWNOUT,NOLVP
Ttelmah
Guest
PostPosted: Fri Aug 24, 2007 4:21 am     Reply with quote
Try something just fractionally different:
Code:

int1 toggle=0;
#define TP1(on) toggle=1;output_bit (PIN_B0, toggle)
#define ToggleTP1() toggle^=1;output_bit (PIN_B0,toggle)


Though the times involved sound to long, and the fact it works on the first pass, suggests this is not the problem, there is always a problem when 'toggling' a pin, that if it hasn't actually reached the logic level expected, the toggle will fail.
It certainly should work...
I presume the final 'requirement', is to do something more complex?. Otherwise, why not use the CCP output pin, and the CCP toggle ability?.

Best Wishes
Ken Johnson



Joined: 23 Mar 2006
Posts: 197
Location: Lewisburg, WV

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PostPosted: Fri Aug 24, 2007 8:55 am     Reply with quote
Thanks guys. I tried running with nodebug - same. Didn't change the toggle stuff, for 2 reasons - the pin does toggle, just at the timer overflow rate, and, timer3 is NOT being reset as I expect. CCP_4 is 5000; Timer3 is 5072 at each interrupt!

There's got to be something trivial (and probably real stupid) with my understanding and setup of the ccp module.

Please look at this code - timer3 is captured at each interrupt, then later printed out. This proves that timer3 is NOT reset. So, what is setup wrong???

Many thanks again for looking at this !
Ken

Code:
//  Filename:   PCH TestCCP.c   Copyright © 2007 K & N Co.
//  Created:    Aug 23, 2007    by Ken Johnson
//  Purpose:

#define CRYSTAL     20000000

#include "18F8722.h"
#device ICD=TRUE
#fuses  DEBUG,NOWDT,PUT

#fuses  HS
#use delay(clock=CRYSTAL,RESTART_WDT)
#use RS232 (DEBUGGER,DISABLE_INTS)

#define CLOCKFREQ   (0.25 * CRYSTAL)    //  Internal clock is 1/4 crystal frequency;
#define TimerCounts(seconds)    ((int16) (CLOCKFREQ * (seconds) + 0.5))
#define TP1(on)         output_bit (PIN_B0, on)
#define ToggleTP1()     output_toggle (PIN_B0)

static  int16   t3[10];

#INT_CCP4
void    CompareISR (void)
{
    static  int16   count;

    ToggleTP1 ();
    if ( count < 10 )
        t3[count++] = get_timer3 ();
}

void    main (void)
{
    int16   n;

    setup_timer_3 (T3_DIV_BY_1 | T3_INTERNAL);
    setup_ccp4 (CCP_COMPARE_RESET_TIMER | CCP_USE_TIMER3);
    TP1 (1);
    set_timer3 (0);                 //  Reset Timer3;
    CCP_4 = (TimerCounts (1e-3));   //  Interrupt at 1 msec;
    clear_interrupt (INT_CCP4);
    enable_interrupts (INT_CCP4);
    enable_interrupts (GLOBAL);

    delay_ms (500);
    printf ("CCP_4 is %lu\n", CCP_4);
    for ( n=0 ; n<10 ; n++ )
        printf ("t3[%lu] %lu\n", n, t3[n]);

    for ( ;; ) {
        delay_ms (250);
    }
}
Ttelmah
Guest
PostPosted: Fri Aug 24, 2007 9:52 am     Reply with quote
Try reading the errata for the chip....
Document 80221c.pdf

I'm afraid it is a hardware fault with the chip, when using this particular mode.

It doesn't apply to the 8720, which was the nearest chip I had that I could test.

Best Wishes
Ken Johnson



Joined: 23 Mar 2006
Posts: 197
Location: Lewisburg, WV

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PostPosted: Fri Aug 24, 2007 11:51 am     Reply with quote
Ttelmah, you've got it ! ! !

I had downloaded and scanned the errata from the Microchip site from the link on the 8722 page, but it's the wrong eratta ! Today I looked up 80221c.pdf from your post and, voila:

"When Timer1 or Timer3 is the time base for CCPx,
and the associated CCPxCON register is configured
with 0x0B (Compare mode, trigger special
event), the assigned timer is not reset on a Special
Event Trigger."

Sheesh - I lost a lot of hair over that one.

Thanks again for your help, folks !

Ken
Ttelmah
Guest
PostPosted: Fri Aug 24, 2007 12:14 pm     Reply with quote
Yes, I too had looked once at the errata, and missed it.
Glad to have actually 'found' the reason, it was annoying me!...

Best Wishes
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